Add clobbersPred - instruction that clobbers condition code / register which are used to predicate instructions.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37465 91177308-0d34-0410-b5e6-96231b3b80d8

1 files changed, 1 insertions, 0 deletions

diff --git a/utils/TableGen/CodeGenTarget.cpp b/utils/TableGen/CodeGenTarget.cpp
index a6677a2bf8..17cea6f2a6 100644
--- a/utils/TableGen/CodeGenTarget.cpp
+++ b/utils/TableGen/CodeGenTarget.cpp
@@ -360,6 +360,7 @@ CodeGenInstruction::CodeGenInstruction(Record *R, const std::string &AsmStr)
   usesCustomDAGSchedInserter = R->getValueAsBit("usesCustomDAGSchedInserter");
   hasCtrlDep   = R->getValueAsBit("hasCtrlDep");
   noResults    = R->getValueAsBit("noResults");
+  clobbersPred = R->getValueAsBit("clobbersPred");
   hasVariableNumberOfOperands = false;
   
   DagInit *DI;