From b5c1c9c8e30d8498cdb2d0ee215f05ca8dc3e4e2 Mon Sep 17 00:00:00 2001 From: Evan Cheng Date: Wed, 6 Jun 2007 10:14:55 +0000 Subject: Add clobbersPred - instruction that clobbers condition code / register which are used to predicate instructions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37465 91177308-0d34-0410-b5e6-96231b3b80d8 --- utils/TableGen/CodeGenTarget.cpp | 1 + 1 file changed, 1 insertion(+) (limited to 'utils/TableGen/CodeGenTarget.cpp') diff --git a/utils/TableGen/CodeGenTarget.cpp b/utils/TableGen/CodeGenTarget.cpp index a6677a2bf8..17cea6f2a6 100644 --- a/utils/TableGen/CodeGenTarget.cpp +++ b/utils/TableGen/CodeGenTarget.cpp @@ -360,6 +360,7 @@ CodeGenInstruction::CodeGenInstruction(Record *R, const std::string &AsmStr) usesCustomDAGSchedInserter = R->getValueAsBit("usesCustomDAGSchedInserter"); hasCtrlDep = R->getValueAsBit("hasCtrlDep"); noResults = R->getValueAsBit("noResults"); + clobbersPred = R->getValueAsBit("clobbersPred"); hasVariableNumberOfOperands = false; DagInit *DI; -- cgit v1.2.3-70-g09d2