diff options
| author | Chris Lattner <sabre@nondot.org> | 2005-10-02 07:07:49 +0000 |
|---|---|---|
| committer | Chris Lattner <sabre@nondot.org> | 2005-10-02 07:07:49 +0000 |
| commit | 43f07a4bbcac695c51def1d0bcd9c9ddb9e6a94d (patch) | |
| tree | 0f1b5df9353a726ccdd8d0a11a0ea95b929df1f4 /lib/Target/PowerPC/PPCISelPattern.cpp | |
| parent | 867940d1b738504a3186276542e94f088821c7f3 (diff) | |
another solution to the fsel issue. Instead of having 4 variants, just force
the comparison to be 64-bits. This is fine because extensions from float
to double are free.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23589 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/PowerPC/PPCISelPattern.cpp')
| -rw-r--r-- | lib/Target/PowerPC/PPCISelPattern.cpp | 15 |
1 files changed, 9 insertions, 6 deletions
diff --git a/lib/Target/PowerPC/PPCISelPattern.cpp b/lib/Target/PowerPC/PPCISelPattern.cpp index 729ffb56ff..5bae7c9280 100644 --- a/lib/Target/PowerPC/PPCISelPattern.cpp +++ b/lib/Target/PowerPC/PPCISelPattern.cpp @@ -815,12 +815,15 @@ unsigned ISel::SelectExpr(SDOperand N, bool Recording) { Tmp1 = SelectExpr(N.getOperand(0)); Tmp2 = SelectExpr(N.getOperand(1)); Tmp3 = SelectExpr(N.getOperand(2)); - if (N.getOperand(0).getValueType() == MVT::f32) - Opc = N.getOperand(0).getValueType() == MVT::f32 ? - PPC::FSELSS : PPC::FSELSD; - else - Opc = N.getOperand(0).getValueType() == MVT::f64 ? - PPC::FSELDD : PPC::FSELDS; + + // Extend the comparison to 64-bits if needed. + if (N.getOperand(0).getValueType() == MVT::f32) { + unsigned Tmp1New = MakeReg(MVT::f64); + BuildMI(BB, PPC::FMRSD, 1, Tmp1New).addReg(Tmp1); + Tmp1 = Tmp1New; + } + + Opc = N.Val->getValueType(0) == MVT::f32 ? PPC::FSELS : PPC::FSELD; BuildMI(BB, Opc, 3, Result).addReg(Tmp1).addReg(Tmp2).addReg(Tmp3); return Result; case PPCISD::FCFID: |