diff options
| author | Chris Lattner <sabre@nondot.org> | 2005-10-02 06:58:23 +0000 |
|---|---|---|
| committer | Chris Lattner <sabre@nondot.org> | 2005-10-02 06:58:23 +0000 |
| commit | 867940d1b738504a3186276542e94f088821c7f3 (patch) | |
| tree | ad702c6d101bff68318407dc6cb88bf749e476bc /lib/Target/PowerPC/PPCISelPattern.cpp | |
| parent | 7c0d664c2118d1c5da50b137856d4a6b1c962ec3 (diff) | |
fsel can take a different FP type for the comparison and for the result. As such
split the FSEL family into 4 things instead of just two.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23588 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/PowerPC/PPCISelPattern.cpp')
| -rw-r--r-- | lib/Target/PowerPC/PPCISelPattern.cpp | 7 |
1 files changed, 5 insertions, 2 deletions
diff --git a/lib/Target/PowerPC/PPCISelPattern.cpp b/lib/Target/PowerPC/PPCISelPattern.cpp index 057104999d..729ffb56ff 100644 --- a/lib/Target/PowerPC/PPCISelPattern.cpp +++ b/lib/Target/PowerPC/PPCISelPattern.cpp @@ -816,9 +816,12 @@ unsigned ISel::SelectExpr(SDOperand N, bool Recording) { Tmp2 = SelectExpr(N.getOperand(1)); Tmp3 = SelectExpr(N.getOperand(2)); if (N.getOperand(0).getValueType() == MVT::f32) - BuildMI(BB, PPC::FSELS, 3, Result).addReg(Tmp1).addReg(Tmp2).addReg(Tmp3); + Opc = N.getOperand(0).getValueType() == MVT::f32 ? + PPC::FSELSS : PPC::FSELSD; else - BuildMI(BB, PPC::FSELD, 3, Result).addReg(Tmp1).addReg(Tmp2).addReg(Tmp3); + Opc = N.getOperand(0).getValueType() == MVT::f64 ? + PPC::FSELDD : PPC::FSELDS; + BuildMI(BB, Opc, 3, Result).addReg(Tmp1).addReg(Tmp2).addReg(Tmp3); return Result; case PPCISD::FCFID: Tmp1 = SelectExpr(N.getOperand(0)); |