diff options
| author | Jiangning Liu <jiangning.liu@arm.com> | 2012-08-02 08:21:27 +0000 |
|---|---|---|
| committer | Jiangning Liu <jiangning.liu@arm.com> | 2012-08-02 08:21:27 +0000 |
| commit | c1b7ca5ba28ded2d83ae534c8e072c2538d43295 (patch) | |
| tree | 8e16398e07d0ce3dee1067da6f6a69cb38f44345 /lib/Target/ARM/Disassembler | |
| parent | 1fb27eccf5b7eabde9678d84411eb1df8a693683 (diff) | |
Fix #13138, a bug around ARM instruction DSB encoding and decoding issue.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161161 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/ARM/Disassembler')
| -rw-r--r-- | lib/Target/ARM/Disassembler/ARMDisassembler.cpp | 13 |
1 files changed, 1 insertions, 12 deletions
diff --git a/lib/Target/ARM/Disassembler/ARMDisassembler.cpp b/lib/Target/ARM/Disassembler/ARMDisassembler.cpp index 47cca2aef0..6f36dcc1ef 100644 --- a/lib/Target/ARM/Disassembler/ARMDisassembler.cpp +++ b/lib/Target/ARM/Disassembler/ARMDisassembler.cpp @@ -3494,19 +3494,8 @@ static DecodeStatus DecodeThumbBLTargetOperand(MCInst &Inst, unsigned Val, static DecodeStatus DecodeMemBarrierOption(MCInst &Inst, unsigned Val, uint64_t Address, const void *Decoder) { - switch (Val) { - default: + if (Val & ~0xf) return MCDisassembler::Fail; - case 0xF: // SY - case 0xE: // ST - case 0xB: // ISH - case 0xA: // ISHST - case 0x7: // NSH - case 0x6: // NSHST - case 0x3: // OSH - case 0x2: // OSHST - break; - } Inst.addOperand(MCOperand::CreateImm(Val)); return MCDisassembler::Success; |