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| author | Richard Barton <richard.barton@arm.com> | 2012-07-09 18:20:02 +0000 |
|---|---|---|
| committer | Richard Barton <richard.barton@arm.com> | 2012-07-09 18:20:02 +0000 |
| commit | 83cfff6229c4afe9af9d48d4109df9a503233a7c (patch) | |
| tree | d587a73eb06d2edfe4062601303db7ab6d1fef34 /lib/Target/ARM/Disassembler | |
| parent | 2e7e34ba5485320a84ca69c83d242e24433f7acd (diff) | |
Oops - correct broken disassembly for VMOV
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159945 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/ARM/Disassembler')
| -rw-r--r-- | lib/Target/ARM/Disassembler/ARMDisassembler.cpp | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/lib/Target/ARM/Disassembler/ARMDisassembler.cpp b/lib/Target/ARM/Disassembler/ARMDisassembler.cpp index 8164e90d0a..c42edd5395 100644 --- a/lib/Target/ARM/Disassembler/ARMDisassembler.cpp +++ b/lib/Target/ARM/Disassembler/ARMDisassembler.cpp @@ -4226,7 +4226,7 @@ static DecodeStatus DecodeVMOVRRS(MCInst &Inst, unsigned Insn, unsigned Rt2 = fieldFromInstruction32(Insn, 16, 4); unsigned Rm = fieldFromInstruction32(Insn, 5, 1); unsigned pred = fieldFromInstruction32(Insn, 28, 4); - Rm |= fieldFromInstruction32(Insn, 0, 4) << 4; + Rm |= fieldFromInstruction32(Insn, 0, 4) << 1; if (Rt == 0xF || Rt2 == 0xF || Rm == 0x1F) S = MCDisassembler::SoftFail; |