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| author | Nate Begeman <natebegeman@mac.com> | 2005-08-31 00:43:49 +0000 |
|---|---|---|
| committer | Nate Begeman <natebegeman@mac.com> | 2005-08-31 00:43:49 +0000 |
| commit | fe75a2836abd15557cf21a5cc34a7048cbba654f (patch) | |
| tree | 725148a0ef48e20882967630ba513b91473e5b22 /lib/CodeGen/SelectionDAG/SelectionDAG.cpp | |
| parent | 9f52f2838d99774d3262bfce7b22d70a7a3f0196 (diff) | |
Sigh, not my day. Fix typo.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23166 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/CodeGen/SelectionDAG/SelectionDAG.cpp')
| -rw-r--r-- | lib/CodeGen/SelectionDAG/SelectionDAG.cpp | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/lib/CodeGen/SelectionDAG/SelectionDAG.cpp b/lib/CodeGen/SelectionDAG/SelectionDAG.cpp index aeacfd5688..a44854e9e8 100644 --- a/lib/CodeGen/SelectionDAG/SelectionDAG.cpp +++ b/lib/CodeGen/SelectionDAG/SelectionDAG.cpp @@ -1099,7 +1099,7 @@ static bool MaskedValueIsZero(const SDOperand &Op, uint64_t Mask, return MaskedValueIsZero(Op.getOperand(0),Mask & ((1ULL << SrcBits)-1),TLI); case ISD::AssertZext: SrcBits = MVT::getSizeInBits(cast<VTSDNode>(Op.getOperand(1))->getVT()); - return (Mask & ((1ULL << SrcBits)-1) == 0; // Returning only the zext bits. + return (Mask & ((1ULL << SrcBits)-1)) == 0; // Returning only the zext bits. case ISD::AND: // (X & C1) & C2 == 0 iff C1 & C2 == 0. if (ConstantSDNode *AndRHS = dyn_cast<ConstantSDNode>(Op.getOperand(1))) |