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| author | Nate Begeman <natebegeman@mac.com> | 2005-08-31 00:43:08 +0000 |
|---|---|---|
| committer | Nate Begeman <natebegeman@mac.com> | 2005-08-31 00:43:08 +0000 |
| commit | 9f52f2838d99774d3262bfce7b22d70a7a3f0196 (patch) | |
| tree | c4f0cbd46b2b39cfa915411e34696abe58cc3dba /lib/CodeGen/SelectionDAG/SelectionDAG.cpp | |
| parent | b85dfab8898807d592ea96acf19f41ebcd9e8813 (diff) | |
Fix a mistake in my previous patch pointed out by sabre; the AssertZext
case in MaskedValueIsZero was wrong.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23165 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/CodeGen/SelectionDAG/SelectionDAG.cpp')
| -rw-r--r-- | lib/CodeGen/SelectionDAG/SelectionDAG.cpp | 5 |
1 files changed, 3 insertions, 2 deletions
diff --git a/lib/CodeGen/SelectionDAG/SelectionDAG.cpp b/lib/CodeGen/SelectionDAG/SelectionDAG.cpp index c550e68e83..aeacfd5688 100644 --- a/lib/CodeGen/SelectionDAG/SelectionDAG.cpp +++ b/lib/CodeGen/SelectionDAG/SelectionDAG.cpp @@ -1095,10 +1095,11 @@ static bool MaskedValueIsZero(const SDOperand &Op, uint64_t Mask, SrcBits = MVT::getSizeInBits(cast<VTSDNode>(Op.getOperand(3))->getVT()); return (Mask & ((1ULL << SrcBits)-1)) == 0; // Returning only the zext bits. case ISD::ZERO_EXTEND: - case ISD::AssertZext: SrcBits = MVT::getSizeInBits(Op.getOperand(0).getValueType()); return MaskedValueIsZero(Op.getOperand(0),Mask & ((1ULL << SrcBits)-1),TLI); - + case ISD::AssertZext: + SrcBits = MVT::getSizeInBits(cast<VTSDNode>(Op.getOperand(1))->getVT()); + return (Mask & ((1ULL << SrcBits)-1) == 0; // Returning only the zext bits. case ISD::AND: // (X & C1) & C2 == 0 iff C1 & C2 == 0. if (ConstantSDNode *AndRHS = dyn_cast<ConstantSDNode>(Op.getOperand(1))) |