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#
# M0+ devices only have SW-DP, but swj-dp code works, just don't
# set any jtag related features
#
source [find target/swj-dp.tcl]
source [find mem_helper.tcl]
if { [info exists CHIPNAME] } {
set _CHIPNAME $CHIPNAME
} else {
set _CHIPNAME stm32l0
}
set _ENDIAN little
# Work-area is a space in RAM used for flash programming
# By default use 8kB (max ram on smallest part)
if { [info exists WORKAREASIZE] } {
set _WORKAREASIZE $WORKAREASIZE
} else {
set _WORKAREASIZE 0x2000
}
# JTAG speed should be <= F_CPU/6.
# F_CPU after reset is ~2MHz, so use F_JTAG max = 333kHz
adapter_khz 300
adapter_nsrst_delay 100
if { [info exists CPUTAPID] } {
set _CPUTAPID $CPUTAPID
} else {
# Arm, m0+, non-multidrop.
# http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.faqs/ka16088.html
set _CPUTAPID 0x0bc11477
}
swj_newdap $_CHIPNAME cpu -expected-id $_CPUTAPID
set _TARGETNAME $_CHIPNAME.cpu
target create $_TARGETNAME cortex_m -endian $_ENDIAN -chain-position $_TARGETNAME
$_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE -work-area-backup 0
# flash size will be probed
set _FLASHNAME $_CHIPNAME.flash
flash bank $_FLASHNAME stm32lx 0x08000000 0 0 0 $_TARGETNAME
reset_config srst_nogate
if {![using_hla]} {
# if srst is not fitted use SYSRESETREQ to
# perform a soft reset
cortex_m reset_config sysresetreq
}
proc stm32l0_enable_HSI16 {} {
# Enable HSI16 as clock source
echo "STM32L0: Enabling HSI16"
# Set HSI16ON in RCC_CR (leave MSI enabled)
mww 0x40021000 0x00000101
# Set HSI16 as SYSCLK (RCC_CFGR)
mww 0x4002100c 0x00000001
# Increase speed
adapter_khz 2500
}
$_TARGETNAME configure -event reset-init {
stm32l0_enable_HSI16
}
$_TARGETNAME configure -event reset-start {
adapter_khz 300
}
$_TARGETNAME configure -event examine-end {
# DBGMCU_CR |= DBG_STANDBY | DBG_STOP | DBG_SLEEP
mmw 0x40015804 0x00000007 0
# Stop watchdog counters during halt
# DBGMCU_APB1_FZ |= DBG_IWDG_STOP | DBG_WWDG_STOP
mmw 0x40015808 0x00001800 0
}
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