1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
|
# The Atheros AR9331 is a highly integrated and cost effective
# IEEE 802.11n 1x1 2.4 GHz System- on-a-Chip (SoC) for wireless
# local area network (WLAN) AP and router platforms.
#
# Notes:
# - MIPS Processor ID (PRId): 0x00019374
# - 24Kc MIPS processor with 64 KB I-Cache and 32 KB D-Cache,
# operating at up to 400 MHz
# - External 16-bit DDR1, DDR2, or SDRAM memory interface
# - TRST is not available.
# - EJTAG PrRst signal is not supported
# - RESET_L pin A72 on the SoC will reset internal JTAG logic.
#
# Pins related for debug and bootstrap:
# Name Pin Description
# JTAG
# JTAG_TCK GPIO0, (A27) Software configurable, default JTAG
# JTAG_TDI GPIO6, (B46) Software configurable, default JTAG
# JTAG_TDO GPIO7, (A54) Software configurable, default JTAG
# JTAG_TMS GPIO8, (A52) Software configurable, default JTAG
# Reset
# RESET_L -, (A72) Input only
# SYS_RST_L ???????? Output reset request or GPIO
# Bootstrap
# MEM_TYPE[1] GPIO28, (A74) 0 - SDRAM, 1 - DDR1 RAM, 2 - DDR2 RAM
# MEM_TYPE[0] GPIO12, (A56)
# FW_DOWNLOAD GPIO16, (A75) Used if BOOT_FROM_SPI = 0. 0 - boot from USB
# 1 - boot from MDIO.
# JTAG_MODE(JS) GPIO11, (B48) 0 - JTAG (Default); 1 - EJTAG
# BOOT_FROM_SPI GPIO1, (A77) 0 - ROM boot; 1 - SPI boot
# SEL_25M_40M GPIO0, (A78) 0 - 25MHz; 1 - 40MHz
# UART
# UART0_SOUT GPIO10, (A79)
# UART0_SIN GPIO9, (B68)
# Per default we need to use "none" variant to be able properly "reset init"
# or "reset halt" the CPU.
reset_config none srst_pulls_trst
# For SRST based variant we still need proper timings.
# For ETH part the reset should be asserted at least for 10ms
# Since there is no other information let's take 100ms to be sure.
adapter srst pulse_width 100
# according to the SoC documentation it should take at least 5ms from
# reset end till bootstrap end. In the practice we need 8ms to get JTAG back
# to live.
adapter srst delay 8
if { [info exists CHIPNAME] } {
set _CHIPNAME $_CHIPNAME
} else {
set _CHIPNAME ar9331
}
jtag newtap $_CHIPNAME cpu -irlen 5 -expected-id 0x00000001
set _TARGETNAME $_CHIPNAME.cpu
target create $_TARGETNAME mips_m4k -endian big -chain-position $_TARGETNAME
# provide watchdog helper.
proc disable_watchdog { } {
mww 0xb8060008 0x0
}
$_TARGETNAME configure -event halted { disable_watchdog }
# Since PrRst is not supported and SRST will reset complete chip
# with JTAG engine, we need to reset CPU from CPU itself.
$_TARGETNAME configure -event reset-assert-pre {
halt
}
$_TARGETNAME configure -event reset-assert {
catch "mww 0xb806001C 0x01000000"
}
# To be able to trigger complete chip reset, in case JTAG is blocked
# or CPU not responding, we still can use this helper.
proc full_reset { } {
reset_config srst_only
reset
halt
reset_config none
}
proc disable_watchdog { } {
;# disable watchdog
mww 0xb8060008 0x0
}
$_TARGETNAME configure -event reset-end { disable_watchdog }
# Section with helpers which can be used by boards
proc ar9331_25mhz_pll_init {} {
mww 0xb8050008 0x00018004 ;# bypass PLL; AHB_POST_DIV - ratio 4
mww 0xb8050004 0x00000352 ;# 34000(ns)/40ns(25MHz) = 0x352 (850)
mww 0xb8050000 0x40818000 ;# Power down control for CPU PLL
;# OUTDIV | REFDIV | DIV_INT
mww 0xb8050010 0x001003e8 ;# CPU PLL Dither FRAC Register
;# (disabled?)
mww 0xb8050000 0x00818000 ;# Power on | OUTDIV | REFDIV | DIV_INT
mww 0xb8050008 0x00008000 ;# remove bypass;
;# AHB_POST_DIV - ratio 2
}
proc ar9331_ddr1_init {} {
mww 0xb8000000 0x7fbc8cd0 ;# DDR_CONFIG - lots of DRAM confs
mww 0xb8000004 0x9dd0e6a8 ;# DDR_CONFIG2 - more DRAM confs
mww 0xb8000010 0x8 ;# Forces a PRECHARGE ALL cycle
mww 0xb8000008 0x133 ;# mode reg: 0x133 - default
mww 0xb8000010 0x1 ;# Forces an MRS update cycl
mww 0xb800000c 0x2 ;# Extended mode register value.
;# default 0x2 - Reset to weak driver, DLL on
mww 0xb8000010 0x2 ;# Forces an EMRS update cycle
mww 0xb8000010 0x8 ;# Forces a PRECHARGE ALL cycle
mww 0xb8000008 0x33 ;# mode reg: remove some bit?
mww 0xb8000010 0x1 ;# Forces an MRS update cycl
mww 0xb8000014 0x4186 ;# enable refres: bit(14) - set refresh rate
mww 0xb800001c 0x8 ;# This register is used along with DQ Lane 0,
;# DQ[7:0], DQS_0
mww 0xb8000020 0x9 ;# This register is used along with DQ Lane 1,
;# DQ[15:8], DQS_1.
mww 0xb8000018 0xff ;# DDR read and capture bit mask.
;# Each bit represents a cycle of valid data.
}
proc ar9331_ddr2_init {} {
mww 0xb8000000 0x7fbc8cd0 ;# DDR_CONFIG - lots of DRAM confs
mww 0xb8000004 0x9dd0e6a8 ;# DDR_CONFIG2 - more DRAM confs
mww 0xb800008c 0x00000a59
mww 0xb8000010 0x00000008 ;# PRECHARGE ALL cycle
mww 0xb8000090 0x00000000
mww 0xb8000010 0x00000010 ;# EMR2S update cycle
mww 0xb8000094 0x00000000
mww 0xb8000010 0x00000020 ;# EMR3S update cycle
mww 0xb800000c 0x00000000
mww 0xb8000010 0x00000002 ;# EMRS update cycle
mww 0xb8000008 0x00000100
mww 0xb8000010 0x00000001 ;# MRS update cycle
mww 0xb8000010 0x00000008 ;# PRECHARGE ALL cycle
mww 0xb8000010 0x00000004
mww 0xb8000010 0x00000004 ;# AUTO REFRESH cycle
mww 0xb8000008 0x00000a33
mww 0xb8000010 0x00000001 ;# MRS update cycle
mww 0xb800000c 0x00000382
mww 0xb8000010 0x00000002 ;# EMRS update cycle
mww 0xb800000c 0x00000402
mww 0xb8000010 0x00000002 ;# EMRS update cycle
mww 0xb8000014 0x00004186 ;# DDR_REFRESH
mww 0xb800001c 0x00000008 ;# DDR_TAP_CTRL0
mww 0xb8000020 0x00000009 ;# DDR_TAP_CTRL1
;# DDR read and capture bit mask.
;# Each bit represents a cycle of valid data.
;# 0xff: use 16-bit DDR
mww 0xb8000018 0x000000ff
}
|
