aboutsummaryrefslogtreecommitdiff
path: root/tcl/board/at91sam9g20-ek.cfg
blob: 773c8899a12c65e0069b01ba95a5d2a289753a47 (plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
#################################################################################################
#												#
# Author: Gary Carlson (gcarlson@carlson-minot.com)						#
# Generated for Atmel AT91SAM9G20-EK evaluation board using Atmel SAM-ICE (J-Link) version 8.	#
#												#
#################################################################################################

# FIXME use some standard target config, maybe create one from this
#
#	source [find target/...cfg]

source [find target/at91sam9g20.cfg]

set _FLASHTYPE nandflash_cs3

# Set reset type.  Note that the AT91SAM9G20-EK board has the trst signal disconnected.  Therefore
# the reset needs to be configured for "srst_only".  If for some reason, a zero-ohm jumper is
# added to the board to connect the trst signal, then this parameter may need to be changed.

reset_config srst_only

adapter srst delay 200
jtag_ntrst_delay 200

# If you don't want to execute built-in boot rom code (and there are good reasons at times not to do that) in the
# AT91SAM9 family, the microcontroller is a lump on a log without initialization.  Because this family has
# some powerful features, we want to have a special function that handles "reset init".  To do this we declare
# an event handler where these special activities can take place.

scan_chain
$_TARGETNAME configure -event reset-init {at91sam9g20_reset_init}
$_TARGETNAME configure -event reset-start {at91sam9g20_reset_start}

# NandFlash configuration and definition

nand device nandflash_cs3 at91sam9 $_TARGETNAME 0x40000000 0xfffffe800
at91sam9 cle 0 22
at91sam9 ale 0 21
at91sam9 rdy_busy 0 0xfffff800 13
at91sam9 ce 0 0xfffff800 14

proc read_register {register} {
        set result ""
        mem2array result 32 $register 1
        return $result(0)
}

proc at91sam9g20_reset_start { } {

	# Make sure that the the jtag is running slow, since there are a number of different ways the board
	# can be configured coming into this state that can cause communication problems with the jtag
	# adapter.  Also since this call can be made following a "reset init" where fast memory accesses
	# are enabled, need to temporarily shut this down so that the RSTC_MR register can be written at slower
	# jtag speed without causing GDB keep alive problem.

	arm7_9 fast_memory_access disable
	adapter speed 2                 ;# Slow-speed oscillator enabled at reset, so run jtag speed slow.
	halt                            ;# Make sure processor is halted, or error will result in following steps.
	wait_halt 10000
	mww 0xfffffd08 0xa5000501       ;# RSTC_MR : enable user reset.
}

proc at91sam9g20_reset_init { } {

	# At reset AT91SAM9G20 chip runs on slow clock (32.768 kHz).  To shift over to a normal clock requires
	# a number of steps that must be carefully performed.  The process outline below follows the
	# recommended procedure outlined in the AT91SAM9G20 technical manual.
	#
	# Several key and very important things to keep in mind:
	# The SDRAM parts used currently on the Atmel evaluation board are -75 grade parts.  This
	# means the master clock (MCLK) must be at or below 133 MHz or timing errors will occur.  The processor
	# core can operate up to 400 MHz and therefore PCLK must be at or below this to function properly.

	mww 0xfffffd44 0x00008000	;# WDT_MR : disable watchdog.

	# Enable the main 18.432 MHz oscillator in CKGR_MOR register.
	# Wait for MOSCS in PMC_SR to assert indicating oscillator is again stable after change to CKGR_MOR.

	mww 0xfffffc20 0x00004001
	while { [expr [read_register 0xfffffc68] & 0x01] != 1 } { sleep 1 }

	# Set PLLA Register for 792.576 MHz (divider: bypass, multiplier: 43).
	# Wait for LOCKA signal in PMC_SR to assert indicating PLLA is stable.

	mww 0xfffffc28 0x202a3f01
	while { [expr [read_register 0xfffffc68] & 0x02] != 2 } { sleep 1 }

	# Set master system clock prescaler divide by 6 and processor clock divide by 2 in PMC_MCKR.
	# Wait for MCKRDY signal from PMC_SR to assert.

	mww 0xfffffc30 0x00000101
	while { [expr [read_register 0xfffffc68] & 0x08] != 8 } { sleep 1 }

	# Now change PMC_MCKR register to select PLLA.
	# Wait for MCKRDY signal from PMC_SR to assert.

	mww 0xfffffc30 0x00001302
	while { [expr [read_register 0xfffffc68] & 0x08] != 8 } { sleep 1 }

	# Processor and master clocks are now operating and stable at maximum frequency possible:
	#	-> MCLK = 132.096 MHz
	#	-> PCLK = 396.288 MHz

	# Switch over to adaptive clocking.

	adapter speed 0

	# Enable faster DCC downloads and memory accesses.

	arm7_9 dcc_downloads enable
	arm7_9 fast_memory_access enable

	# To be able to use external SDRAM, several peripheral configuration registers must
	# be modified.  The first change is made to PIO_ASR to select peripheral functions
	# for D15 through D31.  The second change is made to the PIO_PDR register to disable
	# this for D15 through D31.

	mww 0xfffff870 0xffff0000
	mww 0xfffff804 0xffff0000

	# The EBI chip select register EBI_CS must be specifically configured to enable the internal SDRAM controller
	# using CS1.  Additionally we want CS3 assigned to NandFlash.  Also VDDIO is connected physically on
	# the board to the 3.3 VDC power supply so set the appropriate register bit to notify the micrcontroller.

	mww 0xffffef1c 0x000100a

	# The AT91SAM9G20-EK evaluation board has built-in NandFlash.  The exact physical timing characteristics
	# for the memory type used on the current board (MT29F2G08AACWP) can be established by setting
	# a number of registers.  The first step involves setting up the general I/O pins on the processor
	# to be able to interface and support the external memory.

	mww 0xfffffc10 0x00000010	;# PMC_PCER : enable PIOC clock
	mww 0xfffff800 0x00006000	;# PIOC_PER : enable PIO function for 13(RDY/~BSY) and 14(~CS)
	mww 0xfffff810 0x00004000	;# PIOC_OER : enable output on 14
	mww 0xfffff814 0x00002000	;# PIOC_ODR : disable output on 13
    	mww 0xfffff830 0x00004000	;# PIOC_SODR : set 14 to disable NAND

	# The exact physical timing characteristics for the memory type used on the current board
	# (MT29F2G08AACWP) can be established by setting four registers in order:  SMC_SETUP3,
	# SMC_PULSE3, SMC_CYCLE3, and SMC_MODE3.  Computing the exact values of these registers
	# is a little tedious to do here.  If you have questions about how to do this, Atmel has
	# a decent application note #6255B that covers this process. 

	mww 0xffffec30 0x00020002	;# SMC_SETUP3 : 2 clock cycle setup for NRD and NWE
	mww 0xffffec34 0x04040404	;# SMC_PULSE3 : 4 clock cycle pulse for all signals
	mww 0xffffec38 0x00070006	;# SMC_CYCLE3 : 7 clock cycle NRD and 6 NWE cycle
	mww 0xffffec3C 0x00020003	;# SMC_MODE3 : NRD and NWE control, no NWAIT, 8-bit DBW, 
   
	mww 0xffffe800 0x00000001	;# ECC_CR : reset the ECC parity registers
	mww 0xffffe804 0x00000002	;# ECC_MR : page size is 2112 words (word is 8 bits)

	# Identify NandFlash bank 0.

	nand probe nandflash_cs3

	# The AT91SAM9G20-EK evaluation board has build-in serial data flash also.

	# Now setup SDRAM.  This is tricky and configuration is very important for reliability!  The current calculations
	# are based on 2 x Micron MT48LC16M16A2-75 memory (4 M x 16 bit x 4 banks).  If you use this file as a reference
	# for a new board that uses different SDRAM devices or clock rates, you need to recalculate the value inserted
	# into the SDRAM_CR register.  Using the memory datasheet for the -75 grade part and assuming a master clock
	# of 132.096 MHz then the SDCLK period is equal to 7.6 ns.  This means the device requires:
	#
	#	CAS latency = 3 cycles
	#	TXSR = 10 cycles
	#	TRAS = 6 cycles
	#	TRCD = 3 cycles
	#	TRP = 3 cycles
	#	TRC = 9 cycles
	#	TWR = 2 cycles
	#	9 column, 13 row, 4 banks
	#	refresh equal to or less then 7.8 us for commerical/industrial rated devices
	#
	#	Thus SDRAM_CR = 0xa6339279

	mww 0xffffea08 0xa6339279

	# Next issue a 'NOP' command through the SDRAMC_MR register followed by writing a zero value into
	# the starting memory location for the SDRAM.

	mww 0xffffea00 0x00000001
	mww 0x20000000 0

	# Issue an 'All Banks Precharge' command through the SDRAMC_MR register followed by writing a zero
	# value into the starting memory location for the SDRAM.

	mww 0xffffea00 0x00000002
	mww 0x20000000 0

	# Now issue an 'Auto-Refresh' command through the SDRAMC_MR register.  Follow this operation by writing
	# zero values eight times into the starting memory location for the SDRAM.

	mww 0xffffea00 0x4
	mww 0x20000000 0
	mww 0x20000000 0
	mww 0x20000000 0
	mww 0x20000000 0
	mww 0x20000000 0
	mww 0x20000000 0
	mww 0x20000000 0
	mww 0x20000000 0

	# Almost done, so next issue a 'Load Mode Register' command followed by a zero value write to the
	# the starting memory location for the SDRAM.

	mww 0xffffea00 0x3
	mww 0x20000000 0

	# Signal normal mode using the SDRAMC_MR register and follow with a zero value write the the starting
	# memory location for the SDRAM.

	mww 0xffffea00 0x0
	mww 0x20000000 0

	# Finally set the refresh rate to about every 7 us (7.5 ns x 924 cycles).

	mww 0xffffea04 0x0000039c
}