/***************************************************************************
* Copyright (C) 2005 by Dominic Rath *
* Dominic.Rath@gmx.de *
* *
* Copyright (C) 2008 by Spencer Oliver *
* spen@spen-soft.co.uk *
* *
* This program is free software; you can redistribute it and/or modify *
* it under the terms of the GNU General Public License as published by *
* the Free Software Foundation; either version 2 of the License, or *
* (at your option) any later version. *
* *
* This program is distributed in the hope that it will be useful, *
* but WITHOUT ANY WARRANTY; without even the implied warranty of *
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
* GNU General Public License for more details. *
* *
* You should have received a copy of the GNU General Public License *
* along with this program. If not, see <http://www.gnu.org/licenses/>. *
***************************************************************************/
#ifdef HAVE_CONFIG_H
#include "config.h"
#endif
#include "imp.h"
#include <target/arm7_9_common.h>
/* ISC commands */
#define ISC_IDCODE 0xFE
#define ISC_MFG_READ 0x4C
#define ISC_CONFIGURATION 0x07
#define ISC_ENABLE 0x0C
#define ISC_DISABLE 0x0F
#define ISC_NOOP 0x10
#define ISC_ADDRESS_SHIFT 0x11
#define ISC_CLR_STATUS 0x13
#define ISC_PROGRAM 0x20
#define ISC_PROGRAM_SECURITY 0x22
#define ISC_PROGRAM_UC 0x23
#define ISC_ERASE 0x30
#define ISC_READ 0x50
#define ISC_BLANK_CHECK 0x60
/* ISC_DEFAULT bit definitions */
#define ISC_STATUS_SECURITY 0x40
#define ISC_STATUS_INT_ERROR 0x30
#define ISC_STATUS_MODE 0x08
#define ISC_STATUS_BUSY 0x04
#define ISC_STATUS_ERROR 0x03
/* Option bytes definitions */
#define STR9XPEC_OPT_CSMAPBIT 48
#define STR9XPEC_OPT_LVDTHRESBIT 49
#define STR9XPEC_OPT_LVDSELBIT 50
#define STR9XPEC_OPT_LVDWARNBIT 51
#define STR9XPEC_OPT_OTPBIT 63
enum str9xpec_status_codes {
STR9XPEC_INVALID_COMMAND = 1,
STR9XPEC_ISC_SUCCESS = 2,
STR9XPEC_ISC_DISABLED = 3,
STR9XPEC_ISC_INTFAIL = 32,
};
struct str9xpec_flash_controller {
struct jtag_tap *tap;
uint32_t *sector_bits;
int chain_pos;
int isc_enable;
uint8_t options[8];
};
static int str9xpec_erase_area(struct flash_bank *bank, int first, int last);
static int str9xpec_set_address(struct flash_bank *bank, uint8_t sector);
static int str9xpec_write_options(struct flash_bank *bank);
static int str9xpec_set_instr(struct jtag_tap *tap, uint32_t new_instr, tap_state_t end_state)
{
if (tap == NULL)
return ERROR_TARGET_INVALID;
if (buf_get_u32(tap->cur_instr, 0, tap->ir_length) != new_instr) {
struct scan_field field;
field.num_bits = tap->ir_length;
void *t = calloc(DIV_ROUND_UP(field.num_bits, 8), 1);
field.out_value = t;
buf_set_u32(t, 0, field.num_bits, new_instr);
field.in_value = NULL;
jtag_add_ir_scan(tap, &field, end_state);
free(t);
}
return ERROR_OK;
}
static uint8_t str9xpec_isc_status(struct jtag_tap *tap)
{
struct scan_field field;
uint8_t status;
if (str9xpec_set_instr(tap, ISC_NOOP, TAP_IRPAUSE) != ERROR_OK)
return ISC_STATUS_ERROR;
field.num_bits = 8;
field.out_value = NULL;
field.in_value = &status;
jtag_add_dr_scan(tap, 1, &field, TAP_IDLE);
jtag_execute_queue();
LOG_DEBUG("status: 0x%2.2x", status);
if (status & ISC_STATUS_SECURITY)
LOG_INFO("Device Security Bit Set");
return status;
}
static int str9xpec_isc_enable(struct flash_bank *bank)
{
uint8_t status;
struct jtag_tap *tap;
struct str9xpec_flash_controller