path: root/src/flash/nor/ath79.c

/***************************************************************************
 *   Copyright (C) 2015 by Tobias Diedrich                                 *
 *   <ranma+openwrt@tdiedrich.de>                                          *
 *                                                                         *
 *   based on the stmsmi code written by Antonio Borneo                    *
 *   <borneo.antonio@gmail.com>                                            *
 *                                                                         *
 *   This program is free software; you can redistribute it and/or modify  *
 *   it under the terms of the GNU General Public License as published by  *
 *   the Free Software Foundation; either version 2 of the License, or     *
 *   (at your option) any later version.                                   *
 *                                                                         *
 *   This program is distributed in the hope that it will be useful,       *
 *   but WITHOUT ANY WARRANTY; without even the implied warranty of        *
 *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the         *
 *   GNU General Public License for more details.                          *
 *                                                                         *
 *   You should have received a copy of the GNU General Public License     *
 *   along with this program; if not, write to the                         *
 *   Free Software Foundation, Inc.                                        *
 *                                                                         *
 ***************************************************************************/
/*
 * Driver for the Atheros AR7xxx/AR9xxx SPI flash interface.
 *
 * Since no SPI mode register is present, presumably only
 * SPI "mode 3" (CPOL=1 and CPHA=1) is supported.
 *
 * The SPI interface supports up to 3 chip selects, however the SPI flash
 * used for booting the system must be connected to CS0.
 *
 * On boot, the first 4MiB of flash space are memory-mapped into the
 * area bf000000 - bfffffff (4 copies), so the MIPS bootstrap
 * vector bfc00000 is mapped to the beginning of the flash.
 *
 * By writing a 1 to the REMAP_DISABLE bit in the SPI_CONTROL register,
 * the full area of 16MiB is mapped.
 *
 * By writing a 0 to the SPI_FUNCTION_SELECT register (write-only dword
 * register @bf000000), memory mapping is disabled and the SPI registers
 * are exposed to the CPU instead:
 * bf000000 SPI_FUNCTION_SELECT
 * bf000004 SPI_CONTROL
 * bf000008 SPI_IO_CONTROL
 * bf00000c SPI_READ_DATA
 *
 * When not memory-mapped, the SPI interface is essentially bitbanged
 * using SPI_CONTROL and SPI_IO_CONTROL with the only hardware-assistance
 * being the 32bit read-only shift-register SPI_READ_DATA.
 */

#ifdef HAVE_CONFIG_H
#include "config.h"
#endif

#include "imp.h"
#include "spi.h"
#include <jtag/jtag.h>
#include <helper/time_support.h>
#include <helper/types.h>
#include <target/mips32.h>
#include <target/mips32_pracc.h>
#include <target/target.h>

#define BITS_PER_BYTE 8

#define ATH79_REG_FS     0
#define ATH79_REG_CLOCK  4
#define ATH79_REG_WRITE  8
#define ATH79_REG_DATA  12

#define ATH79_SPI_CS_ALLHI 0x70000
#define ATH79_SPI_CS0_HI   0x10000
#define ATH79_SPI_CS1_HI   0x20000
#define ATH79_SPI_CS2_HI   0x40000
#define ATH79_SPI_CE_HI    0x00100
#define ATH79_SPI_DO_HI    0x00001

#define ATH79_XFER_FINAL   0x00000001
#define ATH79_XFER_PARTIAL 0x00000000

/* Timeout in ms */
#define ATH79_MAX_TIMEOUT  (3000)

struct ath79_spi_ctx {
	uint8_t *page_buf;
	int pre_deselect;
	int post_deselect;
};

struct ath79_flash_bank {
	int probed;
	int chipselect;
	uint32_t io_base;
	const struct flash_device *dev;
	struct ath79_spi_ctx spi;
};

struct ath79_target {
	char *name;
	uint32_t tap_idcode;
	uint32_t io_base;
};

static const struct ath79_target target_devices[] = {
	/* name,   tap_idcode, io_base */
	{ "ATH79", 0x00000001, 0xbf000000 },
	{ NULL,    0,          0 }
};

static const uint32_t ath79_chipselects[] = {
	(~ATH79_SPI_CS0_HI & ATH79_SPI_CS_ALLHI),
	(~ATH79_SPI_CS1_HI & ATH79_SPI_CS_ALLHI),
	(~ATH79_SPI_CS2_HI & ATH79_SPI_CS_ALLHI),
};

static void ath79_pracc_addn(struct pracc_queue_info *ctx,
			     const uint32_t *instr,
			     int n)
{
	for (int i = 0; i < n; i++)
		pracc_add(ctx, 0, instr[i]);
}

static int ath79_spi_bitbang_codegen(struct ath79_flash_bank *ath79_info,
				     struct pracc_queue_info *ctx,
				     uint8_t *data, int len,
				     int partial_xfer)
{
	uint32_t cs_high = ATH79_SPI_CS_ALLHI;
	uint32_t cs_low = ath79_chipselects[ath79_info->chipselect];
	uint32_t clock_high = cs_low | ATH79_SPI_CE_HI;
	uint32_t clock_low = cs_low;
	uint32_t pracc_out = 0;
	uint32_t io_base = ath79_info->io_base;

	const uint32_t preamble1[] = {
		/* $15 = MIPS32_PRACC_BASE_ADDR */
		MIPS32_LUI(0, 15, PRACC_UPPER_BASE_ADDR),
		/* $1 = io_base */
		MIPS32_LUI(0, 1, UPPER16(io_base)),
	};
	ath79_pracc_addn(ctx, preamble1, ARRAY_SIZE(preamble1));
	if (ath79_info->spi.pre_deselect) {
		/* Clear deselect flag so we don't deselect again if
		 * this is a partial xfer.
		 */
		ath79_info->spi.pre_deselect = 0;
		const uint32_t pre_deselect[] = {
			/* [$1 + FS] = 1  (enable flash io register access) */
			MIPS32_LUI(0, 2, UPPER16(1)),
			MIPS32_ORI(0, 2, 2, LOWER16(1)),
			MIPS32_SW(0, 2, ATH79_REG_FS, 1),
			/* deselect flash just in case */
			/* $2 = SPI_CS_DIS */
			MIPS32_LUI(0, 2, UPPER16(cs_high)),
			MIPS32_ORI(0, 2, 2, LOWER16(cs_high)),
			/* [$1 + WRITE] = $2 */
			MIPS32_SW(0, 2, ATH79_REG_WRITE, 1),
		};
		ath79_pracc_addn(ctx, pre_deselect, ARRAY_SIZE(pre_deselect));
	}
	const uint32_t preamble2[] = {
		/* t0 = CLOCK_LOW + 0-bit */
		MIPS32_LUI(0, 8, UPPER16((clock_low + 0))),
		MIPS32_ORI(0, 8, 8, LOWER16((clock_low + 0))),
		/* t1 = CLOCK_LOW + 1-bit */
		MIPS32_LUI(0, 9, UPPER16((clock_low + 1))),
		MIPS32_ORI(0, 9, 9, LOWER16((clock_low + 1))),
		/* t2 = CLOCK_HIGH + 0-bit */
		MIPS32_LUI(0, 10, UPPER16((clock_high + 0))),
		MIPS32_ORI(0, 10, 10, LOWER16((clock_high + 0))),
		/* t3 = CLOCK_HIGH + 1-bit */
		MIPS32_LUI(0, 11, UPPER16((clock_high + 1))),
		MIPS32_ORI(0, 11, 11, LOWER16((clock_high + 1))),
	};
	ath79_pracc_addn(ctx, preamble2, ARRAY_SIZE(preamble2));

	for (int i = 0; i < len; i++) {
		uint8_t x = data[i];

		/* Generate bitbang code for one byte, highest bit first .*/
		for (int j = BITS_PER_BYTE - 1; j >= 0; j--)