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2018-11-18target/stm32f7x: clarify reset_config commentChristopher Head
The reset_config line in the config file does not actually set connect_assert_srst (the default is connect_deassert_srst), but it reads as if it does. Clarify that the target is compatible with connect_assert_srst, without suggesting that the file actually sets it to that value. Change-Id: I14e9445ab282d386b5d0055f6adf03d7c8878a8c Signed-off-by: Christopher Head <chead@zaber.com> Reviewed-on: http://openocd.zylin.com/4743 Tested-by: jenkins Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
2018-11-10target/stm32h7x: Fix documentation of reset_configChristopher Head
The stm32h7x.cfg does not specify connect_assert_srst or connect_deassert_srst in its reset_config. The comment claims that it will therefore connect in reset. However, per the manual, the default configuration is actually connect_deassert_srst, not connect_assert_srst. In actual fact, connect_assert_srst does not work on the STM32H7 because, while SRST is asserted, everything on the AXI bus is inaccessible. The CPU core is accessible, but since the examine-end event handler also pokes at the DBGMCU peripheral, that will fail in connect_assert_srst mode. So using connect_deassert_srst is appropriate, so fix the comment accordingly. Change-Id: If3e32e871fb19cc61183bdf911b7c5efd80b62e2 Signed-off-by: Christopher Head <chead@zaber.com> Reviewed-on: http://openocd.zylin.com/4741 Tested-by: jenkins Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
2018-10-31tcl: target: omit apcsw for hlaPaul Fertser
When using stlink for CM7 targets we have to rely on its firmware to do the right thing as direct DAP access is not possible. Change-Id: Ieee69f4eeea5c911f89f060f31ce86ed043bdfd0 Signed-off-by: Paul Fertser <fercerpav@gmail.com> Reviewed-on: http://openocd.zylin.com/4732 Tested-by: jenkins Reviewed-by: Matthias Welwarsky <matthias@welwarsky.de> Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
2018-10-27zynq_7000: Add zynqpl_program commandMoritz Fischer
This allows for programming the PL part of the Xilinx Zynq 7000 Change-Id: I89e86c0f381951091f6948c46802d17d7f1f3500 Signed-off-by: Moritz Fischer <moritz.fischer@ettus.com> Reviewed-on: http://openocd.zylin.com/4177 Tested-by: jenkins Reviewed-by: Matthias Welwarsky <matthias@welwarsky.de>
2018-10-16esirisc: support eSi-RISC targetsSteven Stallion
eSi-RISC is a highly configurable microprocessor architecture for embedded systems provided by EnSilica. This patch adds support for 32-bit targets and also includes an internal flash driver and uC/OS-III RTOS support. This is a non-traditional target and required a number of additional changes to support non-linear register numbers and the 'p' packet in RTOS support for proper integration into EnSilica's GDB port. Change-Id: I59d5c40b3bb2ace1b1a01b2538bfab211adf113f Signed-off-by: Steven Stallion <stallion@squareup.com> Reviewed-on: http://openocd.zylin.com/4660 Tested-by: jenkins Reviewed-by: Matthias Welwarsky <matthias@welwarsky.de>
2018-10-01tcl/target: Add Renesas R-Car Gen3 targetsAdam Bass
Add configuration for the Renesas R-Car Generation 3 targets. These are SoCs with Cortex A57s, A53s, and R7s. All cores are supported. Change-Id: I795233210e4f647a1a2a0adea7c058ae98b5db70 Signed-off-by: Adam Bass <adam.bass@renesas.com> Reviewed-on: http://openocd.zylin.com/4669 Tested-by: jenkins Reviewed-by: Matthias Welwarsky <matthias@welwarsky.de>
2018-09-27target/atsamv: make APCSW cacheableChristopher Head
Change-Id: Ic00d3192642c682f370a6f7f8b70ae29744eb746 Signed-off-by: Christopher Head <chead@zaber.com> Reviewed-on: http://openocd.zylin.com/4678 Tested-by: jenkins Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
2018-09-27target/stm32: make APCSW cacheableChristopher Head
Change-Id: I7c5c9720ded329848647f17db95f845e46c01c19 Signed-off-by: Christopher Head <chead@zaber.com> Reviewed-on: http://openocd.zylin.com/4674 Tested-by: jenkins Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
2018-08-21max32xxx: Support for MAX32XXX devices.Kevin Gillespie
Adding flash programming support for Maxim Integrated MAX32XXX devices. Change-Id: I5b0f57a885f9d813240e4bc2d9f765b743e1cfc3 Signed-off-by: Kevin Gillespie <kgills@gmail.com> Reviewed-on: http://openocd.zylin.com/3543 Tested-by: jenkins Reviewed-by: Ismail H. KOSE <ihkose@gmail.com> Reviewed-by: Tomas Vanek <vanekt@fbl.cz> Reviewed-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>
2018-08-02tcl/target: add Allwinner V3s SoC supportOleksij Rempel
Change-Id: I2459d2b137050985b7301047f9651951d72d9e9e Signed-off-by: Oleksij Rempel <linux@rempel-privat.de> Reviewed-on: http://openocd.zylin.com/4427 Tested-by: jenkins Reviewed-by: Paul Fertser <fercerpav@gmail.com>
2018-08-02tcl/target/stm32f0x: Allow overriding the Flash bank sizeDominik Peklo
Copy & paste from another stm32 target. Change-Id: I0f6cbcec974ce70c23c1850526354106caee1172 Signed-off-by: Dominik Peklo <dom.peklo@gmail.com> Reviewed-on: http://openocd.zylin.com/4575 Tested-by: jenkins Reviewed-by: Matthias Welwarsky <matthias@welwarsky.de>
2018-07-31target|board: Add Intel (Altera) Arria 10 target and related boardOleksij Rempel
Target information about this SoC can be found here: https://www.altera.com/products/fpga/arria-series/arria-10/overview.html Achilles Instant-Development Kit Arria 10 SoC SoM: https://www.reflexces.com/products-solutions/development-kits/arria-10/achilles-instant-development-kit-arria-10-soc-som Change-Id: Id78c741be6a8b7d3a70f37d41088e47ee61b437a Signed-off-by: Oleksij Rempel <o.rempel@pengutronix.de> Reviewed-on: http://openocd.zylin.com/4583 Tested-by: jenkins Reviewed-by: Paul Fertser <fercerpav@gmail.com>
2018-07-31tcl/target/atheros_ar9331: add documentation and extra helpersOleksij Rempel
Sync it with experience gathered on Qualcomm QCA4531 SoC. This chips are in many ways similar. Change-Id: I06b9c85e5985a09a9be3cb6cc0ce3b37695d2e54 Signed-off-by: Oleksij Rempel <linux@rempel-privat.de> Reviewed-on: http://openocd.zylin.com/4423 Tested-by: jenkins Reviewed-by: Paul Fertser <fercerpav@gmail.com>
2018-07-31tcl/target/atheros_ar9331: add DDR2 helperOleksij Rempel
this helper works on many different boards, so it is good to have it in target config Change-Id: I068deac36fdd73dbbcedffc87865cc5b9d992c1d Signed-off-by: Oleksij Rempel <linux@rempel-privat.de> Reviewed-on: http://openocd.zylin.com/4422 Tested-by: jenkins Reviewed-by: Paul Fertser <fercerpav@gmail.com>
2018-07-31tcl/target|board: move common AR9331 code to atheros_ar9331.cfgAntony Pavlov
The ar9331_25mhz_pll_init and ar9331_ddr1_init routines can be used not only for TP-Link MR3020 board, so move them to the common atheros_ar9331.cfg file. Change-Id: I04090856b08151d6bb0f5ef9cc654efae1c81835 Signed-off-by: Antony Pavlov <antonynpavlov@gmail.com> Reviewed-on: http://openocd.zylin.com/2999 Tested-by: jenkins Reviewed-by: Paul Fertser <fercerpav@gmail.com>
2018-07-31tcl/target: add config for Qualcomm QCA4531Oleksij Rempel
The QCA4531 is a two stream (2x2) 802.11b/g/n single-band programmable Wi-Fi System-on-Chip (SoC) for the Internet of Things (IoT). https://www.qualcomm.com/products/qca4531 Change-Id: I58398c00943b005cfaf0ac1eaad92d1fa4e2cba7 Signed-off-by: Oleksij Rempel <linux@rempel-privat.de> Reviewed-on: http://openocd.zylin.com/4405 Tested-by: jenkins Reviewed-by: Paul Fertser <fercerpav@gmail.com>
2018-07-18flash/nor: add support for TI MSP432 devicesEdward Fewell
Added msp432 flash driver to support the TI MSP432P4x and MSP432E4x microcontrollers. Implemented the flash algo helper as used in the TI debug and flash tools. This implemention supports the MSP432E4, Falcon, and Falcon 2M variants. The flash driver automatically detects the connected variant and configures itself appropriately. Added command to mass erase device for consistency with TI tools and added command to unlock the protected BSL region. Tested using MSP432E401Y, MSP432P401R, and MSP432P4111 LaunchPads. Tested with embedded XDS110 debug probe in CMSIS-DAP mode and with external SEGGER J-Link probe. Removed ti_msp432p4xx.cfg file made obsolete by this patch. Change-Id: I3b29d39ccc492524ef2c4a1733f7f9942c2684c0 Signed-off-by: Edward Fewell <efewell@ti.com> Reviewed-on: http://openocd.zylin.com/4153 Tested-by: jenkins Reviewed-by: Matthias Welwarsky <matthias@welwarsky.de> Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
2018-07-14target/stm32f7x: Clear stuck HSE clock with CSSChristopher Head
Change-Id: Ica0025ea465910dd664ab546b66f4f25b271f1f5 Signed-off-by: Christopher Head <chead@zaber.com> Reviewed-on: http://openocd.zylin.com/4570 Tested-by: jenkins Reviewed-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>
2018-07-13tcl: target: Add NXP LS1012A configAndreas Färber
As seen on the FRDM-LS1012A board. Change-Id: Ifc9074b3f7535167b9ded5f544501ec2879f5db7 Signed-off-by: Andreas Färber <afaerber@suse.de> Reviewed-on: http://openocd.zylin.com/4594 Tested-by: jenkins Reviewed-by: Matthias Welwarsky <matthias@welwarsky.de>
2018-06-25tcl/target: Add Renesas R-Car R8A7794 E2 targetMarek Vasut
Add configuration for the Renesas R-Car R8A7794 E2 target. This is an SoC with two Cortex A7 ARMv7a cores, both A7 cores are supported. Change-Id: Ic1c81840e3bfcef8ee1de5acedffae5c83612a5e Signed-off-by: Marek Vasut <marek.vasut@gmail.com> Reviewed-on: http://openocd.zylin.com/4531 Tested-by: jenkins Reviewed-by: Matthias Welwarsky <matthias@welwarsky.de>
2018-06-15tcl/target/stm32f7x: configure faster system clock in reset-initTomas Vanek
STM32F7xx devices need faster clock for flash programming over JTAG transport. Using reset default 16 MHz clock resulted in lot of DAP WAITs and substantial decrease of flashing performance. Adapted to the restructured dap support (see 2231da8ec4e7d7ae9b652f3dd1a7104f5a110f3f). Change-Id: Ida6915331dd924c9c0d08822fd94c04ad408cdc5 Signed-off-by: Tomas Vanek <vanekt@fbl.cz> Reviewed-on: http://openocd.zylin.com/4464 Tested-by: jenkins Reviewed-by: Christopher Head <chead@zaber.com>
2018-06-15flash/nor: Add support for TI CC26xx/CC13xx flashEdward Fewell
Added cc26xx flash driver to support the TI CC26xx and CC13xx microcontrollers. Driver is capable of determining which MCU is connected and configures itself accordingly. Added config files for four specific variants: CC26x0, CC13x0, CC26x2, and CC13x2. Note that the flash loader code is based on the sources used to support flash in Code Composer Studio and Uniflash from TI. Removed cc26xx.cfg file made obsolete by this patch. Change-Id: Ie2b0f74f8af7517a9184704b839677d1c9787862 Signed-off-by: Edward Fewell <efewell@ti.com> Reviewed-on: http://openocd.zylin.com/4358 Tested-by: jenkins Reviewed-by: Tomas Vanek <vanekt@fbl.cz> Reviewed-by: Fredrik Hederstierna <fredrik@hederstierna.com>
2018-06-06psoc5lp: Add NV Latch flash driverAndreas Färber
Erasing is not supported by the hardware, it can be written directly. Tested on CY8CKIT-059, except modifying-write. Change-Id: I6e920ed930dcd5c7f0b10c5b1b4791a828d9080a Signed-off-by: Andreas Färber <afaerber@suse.de> Signed-off-by: Tomas Vanek <vanekt@fbl.cz> Reviewed-on: http://openocd.zylin.com/3434 Tested-by: jenkins
2018-06-06psoc5lp: Add EEPROM flash driverAndreas Färber
Tested on CY8CKIT-059. Change-Id: Ib02262e8eebf0df3d29492b8a7daa65b262da580 Signed-off-by: Andreas Färber <afaerber@suse.de> Signed-off-by: Tomas Vanek <vanekt@fbl.cz> Reviewed-on: http://openocd.zylin.com/3433 Tested-by: jenkins
2018-06-06flash/nor: Add PSoC 5LP flash driverAndreas Färber
Always probe for ECC mode and display ECC sectors if disabled. Non-ECC write is implemented as zeroing the ECC/config bytes. Erasing ECC sectors is ignored, erase-checking takes them into account. Tested with CY8CKIT-059 (CY8C5888), except ECC mode. Change-Id: If63b9ffca7ad8de038be3c086c49712b629ec554 Signed-off-by: Andreas Färber <afaerber@suse.de> Signed-off-by: Tomas Vanek <vanekt@fbl.cz> Signed-off-by: Forest Crossman <cyrozap@gmail.com> Reviewed-on: http://openocd.zylin.com/3432 Tested-by: jenkins
2018-06-06flash/nor: Add support for TI CC3220SF internal flashEdward Fewell
Added cc3220sf flash driver to support the TI CC3220SF microcontrollers. Implemented flash driver to support the internal flash of the CC3220SF. The implementation does not support the serial flash of the CC32xx family that requires connection over UART, and not via JTAG/SWD debug. Added config files for both CC32xx devices (no flash) and CC3220SF (with flash). Updated to implement comments from code review. Additional updates to handle remaining comments from review. Additional updates per review. Added code to only request aligned writes and full 32-bit words down to flash helper algorithm. Updated for recent changes in OpenOCD flash code. Removed cc32xx.cfg file made obsolete by this patch. Change-Id: I58fc1478d07238d39c7ef02339f1097a91668c47 Signed-off-by: Edward Fewell <efewell@ti.com> Reviewed-on: http://openocd.zylin.com/4319 Tested-by: jenkins Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
2018-04-23psoc6: Run flash algorithm asynchronously to improve performanceBohdan Tymkiv
Existing psoc6 driver starts flash algorithm for each Flash row. This is suboptimal from performance point of view, starting/stopping flash algorithm for each row adds significant overhead. This change starts flash algorithm and leaves it running asynchronously while driver performs flash operations. Performance gain is 170...250% depending on probe: flash write_image img_256k.bin | w/o this change | with this change | ----------------------------------|-----------------|------------------| KitProg2/CMSIS-DAP, SWD @ 1 MHz | 4 KiB/s | 10 KiB/s | J-Link Ultra, SWD @ 1 MHz | 17 KiB/s | 31 KiB/s | J-Link Ultra, SWD @ 4 MHz | 33 KiB/s | 57 KiB/s | Change-Id: I5bd582584b35af67600c4d197829eb7aeeec7e3f Signed-off-by: Bohdan Tymkiv <bhdt@cypress.com> Reviewed-on: http://openocd.zylin.com/4472 Tested-by: jenkins Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
2018-04-23board: add configuration for stm32f103c8 "Blue Pill"Matthias Welwarsky
The "Blue Pill" is a popular development board with an STM32F103C8 micro controller. According to sources, it has a 128kB Flash on board even though the option bytes only report 64kB. This patch therefore also modifies target/stm32f1x.cfg to take an optional FLASH_SIZE variable into account which the board file sets to 0x20000. Change-Id: I8a78ccd2b5faf637c539ee3cf8136789ee15c95d Signed-off-by: Matthias Welwarsky <matthias.welwarsky@sysgo.com> Reviewed-on: http://openocd.zylin.com/4495 Tested-by: jenkins Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
2018-04-18tcl/target: Add Renesas R-Car R8A7790 H2 targetMarek Vasut
Add configuration for the Renesas R-Car R8A7790 H2 target. This is an SoC with four Cortex A15 and four Cortex A7 ARMv7a cores, only the four A15 cores are supported. Change-Id: I6099b257cc0f04e6858ed5f5f8c8d8ad82ef7650 Signed-off-by: Marek Vasut <marek.vasut@gmail.com> Reviewed-on: http://openocd.zylin.com/4490 Tested-by: jenkins Reviewed-by: Matthias Welwarsky <matthias@welwarsky.de>
2018-04-12target: add Cortex-M4 target to VF6xx targetMatthias Welwarsky
The Vybrid VF6xx SoCs contain an additional Cortex-M4 core connected to AP number 3 of the main DAP. Change-Id: I59c020fdfc53e909b1f0dac1a8627a62cdaa74f2 Signed-off-by: Matthias Welwarsky <matthias.welwarsky@sysgo.com> Reviewed-on: http://openocd.zylin.com/3640 Tested-by: jenkins Reviewed-by: Matthias Welwarsky <matthias@welwarsky.de>
2018-04-10target: add configuration for NXP MC-IMX8M-EVKMatthias Welwarsky
includes target configuration for i.MX8M SoC family, board file needs to set up CHIPNAME and CHIPCORES to match the actual hardware configuration Change-Id: Ieb6d89cab2477a58f85d0ef9cd242710950191c0 Signed-off-by: Matthias Welwarsky <matthias.welwarsky@sysgo.com> Reviewed-on: http://openocd.zylin.com/4434 Tested-by: jenkins Reviewed-by: Matthias Welwarsky <matthias@welwarsky.de>
2018-04-09tcl/target: Add Renesas R-Car R8A7791 M2W targetNiklas Söderlund
Add configuration for the Renesas R-Car R8A7791 M2W target. This is an SoC with two Cortex A15 ARMv7a cores, both cores are supported. This patch is based on initial submission by Adam Bass and improvements by Niklas Söderlund. Change-Id: I297da62b9ce71ad222a401d98e6bcb8502427673 Signed-off-by: Marek Vasut <marek.vasut@gmail.com> Cc: Adam Bass <adam.bass@renesas.com> Cc: Niklas Söderlund <niklas.soderlund@ragnatech.se> Reviewed-on: http://openocd.zylin.com/4485 Tested-by: jenkins Reviewed-by: Matthias Welwarsky <matthias@welwarsky.de>
2018-03-30target: restructure dap supportMatthias Welwarsky
- add 'dap create' command to create dap instances - move all dap subcmmand into the dap instance commands - keep 'dap info' for convenience - change all armv7 and armv8 targets to take a dap instance instead of a jtag chain position - restructure tap/dap/target relations, jtag tap no longer references the dap, daps are now independently created and initialized. - clean up swd connect - re-initialize DAP also on JTAG errors (e.g. after reset, power cycle) - update documentation - update target files Change-Id: I322cf3969b5407c25d1d3962f9d9b9bc1df067d9 Signed-off-by: Matthias Welwarsky <matthias.welwarsky@sysgo.com> Reviewed-on: http://openocd.zylin.com/4468 Tested-by: jenkins Reviewed-by: Matthias Welwarsky <matthias@welwarsky.de>
2018-03-30tcl/board: add configuration for the avnet ultrazed-eg starter kitMatthias Welwarsky
also contains target configuration for the Xilinx UltraScale+ platform Change-Id: I6300cbc85c1ed71df71d8aaca59500bbf18f0093 Signed-off-by: Matthias Welwarsky <matthias.welwarsky@sysgo.com> Reviewed-on: http://openocd.zylin.com/4467 Tested-by: jenkins Reviewed-by: Matthias Welwarsky <matthias@welwarsky.de>
2018-03-30arm_cti: add cti command groupMatthias Welwarsky
Extend the CTI abstraction to be accessible from TCL and change the 'target' command to accept a cti 'object' instead of a base address. This also allows accessing CTI instances that are not related to a configured target. Change-Id: Iac9ed0edca6f1be00fe93783a35c26077f6bc80a Signed-off-by: Matthias Welwarsky <matthias.welwarsky@sysgo.com> Reviewed-on: http://openocd.zylin.com/4031 Tested-by: jenkins Reviewed-by: Matthias Welwarsky <matthias@welwarsky.de>
2018-03-15tcl/target: warn if a Kinetis MCU is connected to a high level adapterTomas Vanek
Make sure the user is aware he can lock the device though unlock is not possible without access to MDM-AP. Change-Id: I92676530e95d19489c6739748a99c2895849f90f Signed-off-by: Tomas Vanek <vanekt@fbl.cz> Reviewed-on: http://openocd.zylin.com/4403 Tested-by: jenkins
2018-03-07Added support for STMicroelectronics BlueNRG-1 and BlueNRG-2 SoCMichele Sardo
Added configuration files and flash loaders. Change-Id: I768eb3626f4e0eadb206bef90a867cc146fe8c75 Signed-off-by: Michele Sardo <msmttchr@gmail.com> Reviewed-on: http://openocd.zylin.com/4226 Tested-by: jenkins Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
2018-02-24efm32: Add JTAG definitions to EFM32 target fileJonas Norling
This makes it possible to program newer EFM32 and EFR32 chips with JTAG, as opposed to SWD. Change-Id: Ia3e8c1bbc66fc1f33e8cf2087ccf0d1b4dfd74e1 Signed-off-by: Jonas Norling <jonas.norling@cyanconnode.com> Reviewed-on: http://openocd.zylin.com/4262 Tested-by: jenkins Reviewed-by: Fredrik Hederstierna <fredrik@hederstierna.com> Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
2018-02-21icepick-d: extend access to core control registerMatthias Welwarsky
The ICEPick-D jtag router has core control registers that provide the same (or similar) functionality as the tap control register, for individual cores accessible through the same tap (e.g. through a DAP). Core control registers are located at address "0x60 + core-id" of the ROUTER address space (IR=ROUTER). It is sometimes helpful or even necessary to modify the core control register. This patch renames the "icepick_d_coreid" function to the more appropriate "icepick_d_core_control" and adds a "value" argument that allows writing of arbitrary value. "icepick_d_tapenable" is extended by an optional value argument so that core control can be written as the tap is enabled. Change-Id: I0e7f91b596cb5075364c6c233348508f58e0a901 Signed-off-by: Matthias Welwarsky <matthias.welwarsky@sysgo.com> Reviewed-on: http://openocd.zylin.com/4141 Tested-by: jenkins Reviewed-by: Matthias Welwarsky <matthias@welwarsky.de>
2018-02-14Add support for Cypress PSoC6 family of devicesBohdan Tymkiv
* Tested on CY8CKIT-001 kit with PSoC6 daughter board. * Tested with several J-Link adapters (Ultra+, Basic) Change-Id: I0a818c231e5f0b270c7774037b38d23221d59417 Signed-off-by: Bohdan Tymkiv <bhdt@cypress.com> Reviewed-on: http://openocd.zylin.com/4233 Tested-by: jenkins Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
2018-02-14psoc4: update for 4x00BLE, L, M, S and PRoC BLE devicesTomas Vanek
Flash ROM API command PSOC4_CMD_SET_IMO48 is now optional on new devices. Also code tidy up: - improved system ROM call error detection - probe does not require the target to be halted - default_padded_value and erased_value set to 0 - fixed endianess problem in flash write and protection setting - removed fancy chip detection table as it would be updated too often - psoc4 flash_autoerase is now on by default to ease programming psoc4.cfg distinguishes chip family and uses either proprietary acquire function of a KitProg adapter or TEST_MODE workaround to "reset halt" Change-Id: I2c75ec46ed0a95e09274fad70b62d6eed7b9ecdf Signed-off-by: Tomas Vanek <vanekt@fbl.cz> Reviewed-on: http://openocd.zylin.com/3807 Tested-by: jenkins Reviewed-by: David Girault <david.f.girault@gmail.com>
2018-02-01Kinetis_ke: add KEAx family to texi and cfg commentTomas Vanek
Change-Id: Id8f676b027f57fc540473c1a3a01bdd2ec49a200 Signed-off-by: Tomas Vanek <vanekt@fbl.cz> Reviewed-on: http://openocd.zylin.com/4232 Tested-by: jenkins Reviewed-by: Joakim Nohlgård <joakim.nohlgard@eistec.se>
2018-01-25tcl: target: klx: use 1KiB for working areaPaul Fertser
Some parts have only that much. Reported by robertfoos_ on IRC. Change-Id: I684fdccfa62cf726466ddc467543a990fd88c4dc Signed-off-by: Paul Fertser <fercerpav@gmail.com> Reviewed-on: http://openocd.zylin.com/4369 Reviewed-by: Robert Foss <robert.foss@memcpy.io> Tested-by: jenkins Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
2018-01-16target: add initial imx7.cfgOleksij Rempel
Change-Id: I899a215049ff0bc8840463c71018867ef71b5b90 Signed-off-by: Oleksij Rempel <linux@rempel-privat.de> Reviewed-on: http://openocd.zylin.com/4190 Reviewed-by: Matthias Welwarsky <matthias@welwarsky.de> Tested-by: jenkins
2018-01-12Added config files for stm8l152 stm8s003 and stm8s105Ake Rehnman
Change-Id: I26cc401aafac01e5aed8eac605488da5221ffdc2 Signed-off-by: Ake Rehnman <ake.rehnman@gmail.com> Reviewed-on: http://openocd.zylin.com/4268 Tested-by: jenkins Reviewed-by: Paul Fertser <fercerpav@gmail.com>
2017-12-20configs for Marvell Armada 3700Jiri Kastner
Change-Id: I367f39c9bc9e58380d6d5b500d5368d5173d96bd Signed-off-by: Jiri Kastner <cz172638@gmail.com> Signed-off-by: Forest Crossman <cyrozap@gmail.com> Reviewed-on: http://openocd.zylin.com/4302 Tested-by: jenkins Reviewed-by: Paul Fertser <fercerpav@gmail.com>
2017-12-08config: stm32l01x and stm32l02x chips supportelmot
New low-end chips have only 2k of RAM, workarea size adjusted Change-Id: Ibfccd73fef9e6dabffc87d901736c5626ce411fe Signed-off-by: Ilia Motornyi <elijah.mot@gmail.com> Reviewed-on: http://openocd.zylin.com/4308 Tested-by: jenkins Reviewed-by: Karl Palsson <karlp@tweak.net.au> Reviewed-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>
2017-12-07stm8 : new targetAke Rehnman
New STM8 target based mostly on mips4k. Target communication through STLINK/SWIM. No flash driver yet but it is still possible to program flash through load_image command. The usual target debug methods are implemented. Change-Id: I7216f231d3ac7c70cae20f1cd8463c2ed864a329 Signed-off-by: Ake Rehnman <ake.rehnman@gmail.com> Reviewed-on: http://openocd.zylin.com/3953 Tested-by: jenkins Reviewed-by: Tomas Vanek <vanekt@fbl.cz> Reviewed-by: Paul Fertser <fercerpav@gmail.com>
2017-12-06Add STM32H7 config filesAlexandre Torgue
Add 2 target files: -stm32h7x.cfg -stm32h7x_dual_bank.cfg Add 2 config files for: -STM32H743zi-nucleo bord -STM32H743i and STM32H753i eval boards. Change-Id: I2aae2c5acff4f3ff8e1bf232fda5a11a87f71703 Signed-off-by: Alexandre TORGUE <alexandre.torgue@st.com> Reviewed-on: http://openocd.zylin.com/4182 Tested-by: jenkins Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
2017-10-16tcl: add hi3798 target and Tocoding Poplar board configPeter Griffin
This config covers the 4x Cortex A53 CPUs. A custom connector is required from J14 to standard ARM JTAG on v1 boards. However v2 hardware should have a standard FTSH-105-01-L-DV connector. Pinmuxing code to enable JTAG pins is included in l-loader-poplar repository, so board is flashed with open source code, JTAG is available at very early boot. Alternatively the following pokes can be issued from U-Boot to enable JTAG (e.g. to debug hisilicon SDK). mw 0xf8a210ec 0x130; mw 0xf8a210f0 0x130; mw 0xf8a210f4 0x130; mw 0xf8a210f8 0x130; mw 0xf8a210fc 0x130; mw 0xf8a21100 0x130; Change-Id: I2b83dfcb3dc5461c1620f94dd99aa7b31fdda59b Signed-off-by: Peter Griffin <peter.griffin@linaro.org> Reviewed-on: http://openocd.zylin.com/4161 Tested-by: jenkins Reviewed-by: Jiri Kastner <cz172638@gmail.com> Reviewed-by: Paul Fertser <fercerpav@gmail.com>
generated by cgit v1.2.3-18-g5258 (git 2.32.0) at 2024-10-16 16:22:47 +0000