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AgeCommit message (Expand)Author
2015-12-29cortex_a: Find debug base using the detected APB-AP and not AP 1Andreas Fritiofson
2015-12-29arm_adi_v5: Convert the AP references from numbers to pointersAndreas Fritiofson
2015-12-29cortex_m: Discover the AP to use, just like Cortex-AAndreas Fritiofson
2015-12-29cortex_a: Call ahbap_debugport_init on the discovered AP and not 0Andreas Fritiofson
2015-12-29arm_adi_v5: Add a back-pointer from an AP to its DAPAndreas Fritiofson
2015-12-29arm_adi_v5: Remove unused is_swd flagAndreas Fritiofson
2015-12-29target/arm: Remove usage of struct arm_jtag in ARMv7 targetsAndreas Fritiofson
2015-12-29swd: Remove DAP from parameter listAndreas Fritiofson
2015-12-29arm_debug: Support multiple APs per DAP and remove DAP from armv7* structsPatrick Stewart
2015-12-29cortex_m: Select an AP when accessing the DAPPatrick Stewart
2015-12-29adi_v5: return proper value on timeoutAlamy Liu
2015-12-29adi_v5: Rename AP_REG_* to MEM_AP_REG_* and add LA supportAlamy Liu
2015-12-29cortex-a: Fix "Detected core" number is always '0'Alamy Liu
2015-12-01cortex_a: fix fast-mode memory readsMatthias Welwarsky
2015-11-30cortex_a: replace cortex_a_check_address functionMatthias Welwarsky
2015-11-30cortex_a: rework mmu manipulationMatthias Welwarsky
2015-11-30cortex_a: force cache and tlb bypass when cpu is in debug stateMatthias Welwarsky
2015-11-30armv7a: fix-up dcache clean and flush functions inner loop patternMatthias Welwarsky
2015-11-30cortex_a: Update instruction cache after setting a soft breakpointMatthias Welwarsky
2015-11-30armv7a: correctly handle invalidation of inner data cachesMatthias Welwarsky
2015-11-30armv7a: fix debug messages regarding cache on/off stateMatthias Welwarsky
2015-11-30armv7a: rework automatic flush-on-write handlingMatthias Welwarsky
2015-11-30armv7a: add d-cache virtual address range flush functionMatthias Welwarsky
2015-11-30armv7a: remove indirection for cache info handlerMatthias Welwarsky
2015-11-30armv7a: fix handling of inner cachesMatthias Welwarsky
2015-11-30armv7a: remove special l2x flush-all and cache-info handlersMatthias Welwarsky
2015-11-30armv7a: rename l2_cache to outer_cacheMatthias Welwarsky
2015-11-30armv7a: remove l1 flush all data handlerOleksij Rempel
2015-11-30add armv7a_cache handlersOleksij Rempel
2015-11-30cortex_a: add cortex_a_[read|write]_memory_ahbOleksij Rempel
2015-11-30cortex_a: add cortex_a_[read|write]_bufferOleksij Rempel
2015-11-30cortex_a: remove cache handlers from cortex_a_write_phys_memoryOleksij Rempel
2015-11-30cortex_a: remove ahb support for phys_memory accessOleksij Rempel
2015-11-27adi_v5: Fix wrong ap valueAlamy Liu
2015-11-13target: cortex_a: add deinit_target handler to free memoryPaul Fertser
2015-11-07target: cortex_a: do not create new register cache every resetPaul Fertser
2015-11-07Cortex A/R : Allow interrupt disable during single-stepEvan Hunter
2015-11-05armv7a: correct calculation of ttbr0_maskMatthias Welwarsky
2015-11-05armv7a: re-read ttb information if ttbcr changesMatthias Welwarsky
2015-11-03helper/fileio: Use size_t for file size.Marc Schink
2015-11-03target: tell which target state is meantOleksij Rempel
2015-11-03cortex_m: dwt_num_comp should be set to zero in cortex_m_dwt_free()Tomas Vanek
2015-10-30quark: updating license to GPLv2+Ivan De Cesaris
2015-10-30Cortex-M: Detect Flash Patch Revision and implement Rev. 2 handling.Uwe Bonnes
2015-09-30ADIv5: Fix typo in log messageEvan Hunter
2015-09-30armv7m: Fix memory leak in register caching.Marc Schink
2015-09-05server: tcl_trace commandAustin Morton
2015-08-06target/testee: manage target->stateRobert Jordens
2015-08-06target: check memory handlers before use for all typesKarl Palsson
2015-05-17server: avoid the tcl server crashing when there is no targetAustin Morton
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