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2015-11-30cortex_a: replace cortex_a_check_address functionMatthias Welwarsky
When accessing memory through the ARM core, privilege levels and mmu access permissions observed. Thus it depends on the current mode of the ARM core whether an access is possible or not. the ARM in USR mode can not access memory mapped to a higher privilege level. This means, if the ARM core is halted while executing at PL0, the debugger would be prevented from setting a breakpoint at an address with a higher privilege level, e.g. in the OS kernel. This is not desirable. cortex_a_check_address() tried to work around this by predicting if an access would fail and switched the ARM core to SVC mode. However, the prediction was based on hardcoded address ranges and only worked for Linux and a 3G/1G user/kernel space split. This patch changes the policy to always switch to SVC mode for memory accesses. It introduces two functions cortex_a_prep_memaccess() and cortex_a_post_memaccess() which bracket memory reads and writes. These function encapsulate all actions necessary for preparation and cleanup. Change-Id: I4ccdb5fd17eadeb2b66ae28caaf0ccd2d014eaa9 Signed-off-by: Matthias Welwarsky <matthias@welwarsky.de> Reviewed-on: http://openocd.zylin.com/3119 Reviewed-by: Paul Fertser <fercerpav@gmail.com> Tested-by: jenkins
2015-11-30cortex_a: rework mmu manipulationMatthias Welwarsky
when disabling the mmu to access physical addresses, normally the d-cache must be disabled as well. Disabling the d-cache also requires a full clean&invalidate. However, since all memory writes are treated as write- through no-allocate and memory reads do not allocate cache lines, effectively the d-cache state does not change at all. We can therefore save the the d-cache disabling and flushing. This patch also simplifies the function a bit. Change-Id: Ia17c56a28f432156429cd4596107e3652b788e63 Signed-off-by: Matthias Welwarsky <matthias@welwarsky.de> Reviewed-on: http://openocd.zylin.com/3114 Tested-by: jenkins Reviewed-by: Paul Fertser <fercerpav@gmail.com>
2015-11-30cortex_a: force cache and tlb bypass when cpu is in debug stateMatthias Welwarsky
for minimal impact on the hardware state, force all memory accesses to bypass the caches and tlbs. This may actually be the default, but ARM recommends in DDI0406C to set proper default values on debug init. Change-Id: If5ac097b6ee725c047b1e86c2f90eabe16b98c7b Signed-off-by: Matthias Welwarsky <matthias@welwarsky.de> Reviewed-on: http://openocd.zylin.com/3079 Reviewed-by: Paul Fertser <fercerpav@gmail.com> Tested-by: jenkins
2015-11-30cortex_a: Update instruction cache after setting a soft breakpointMatthias Welwarsky
Call armv7a_l1_d_cache_flush_virt() before writing the breakpoint, to make sure the d-cache is clean and invalid at the breakpoint location down to PoC. Call armv7a_l1_d_cache_inval_virt() after writing the breakpoint again, so that d-cache will pick up the modified code. Call armv7a_l1_i_cache_inval_virt() after writing the breakpoint to memory to make the change visible to the CPU. Change-Id: I24fc27058d99cb00d7f6002ccb623cab66b0d234 Signed-off-by: Matthias Welwarsky <matthias@welwarsky.de> Reviewed-on: http://openocd.zylin.com/3033 Reviewed-by: Paul Fertser <fercerpav@gmail.com> Tested-by: jenkins
2015-11-30armv7a: rework automatic flush-on-write handlingMatthias Welwarsky
The following changes are implemented: - Clean&Invalidate the VA range to PoC *before* the write takes place - Remove SMP handling since DCCIMVA instruction already maintains SMP coherence. - Remove separate Invalidate step Change-Id: I19fd3cc226d8ecf2937276fc63258b6a26e369a7 Signed-off-by: Matthias Welwarsky <matthias@welwarsky.de> Reviewed-on: http://openocd.zylin.com/3027 Reviewed-by: Paul Fertser <fercerpav@gmail.com> Tested-by: jenkins
2015-11-30armv7a: fix handling of inner cachesMatthias Welwarsky
ARMv7 architecture allows up to 7 cache levels that are architecturally visible, as opposed to "system caches", which are outside of the domain defined by ARMv7 and require separate management. This patch enables detection and identification of caches at all levels. It also implements a new "flush-all" function that cleans & invalidates all cache levels to the "Point of Coherence". Change-Id: Ib77115d6044d39845907941c6f031e208f6e0aa5 Signed-off-by: Matthias Welwarsky <matthias@welwarsky.de> Reviewed-on: http://openocd.zylin.com/3024 Reviewed-by: Paul Fertser <fercerpav@gmail.com> Tested-by: jenkins
2015-11-30add armv7a_cache handlersOleksij Rempel
This patch introduces, new command set and handlers for l1 and l2x caches. Patch set 10 folded the following changes into this one: Ib1a2a1fc1b929dc49532ac13a78e8eb796ab4415 If8d87a03281d0f4ad402909998e7834eb4837e79 I0749f129fa74e04f4e9c20d143a744f09ef750d8 Change-Id: I849f4d1f20610087885eeddefa81d976f77cf199 Signed-off-by: Oleksij Rempel <linux@rempel-privat.de> Signed-off-by: Matthias Welwarsky <matthias@welwarsky.de> Reviewed-on: http://openocd.zylin.com/2800 Tested-by: jenkins Reviewed-by: Paul Fertser <fercerpav@gmail.com>
2015-11-30cortex_a: add cortex_a_[read|write]_memory_ahbOleksij Rempel
Change-Id: I39c457274e1714a8d42233f7fc490fb58f5cb38e Signed-off-by: Oleksij Rempel <linux@rempel-privat.de> Reviewed-on: http://openocd.zylin.com/2798 Reviewed-by: Paul Fertser <fercerpav@gmail.com> Tested-by: jenkins
2015-11-30cortex_a: add cortex_a_[read|write]_bufferOleksij Rempel
Change-Id: I82011822d913aa7228f5c6262b540156494bedfe Signed-off-by: Oleksij Rempel <linux@rempel-privat.de> Reviewed-on: http://openocd.zylin.com/2797 Reviewed-by: Paul Fertser <fercerpav@gmail.com> Tested-by: jenkins
2015-11-30cortex_a: remove cache handlers from cortex_a_write_phys_memoryOleksij Rempel
This was needed for ahb access Change-Id: I638f45a276a593c08140b5d9d7480617aa85f096 Signed-off-by: Oleksij Rempel <linux@rempel-privat.de> Reviewed-on: http://openocd.zylin.com/2796 Reviewed-by: Paul Fertser <fercerpav@gmail.com> Tested-by: jenkins
2015-11-30cortex_a: remove ahb support for phys_memory accessOleksij Rempel
Change-Id: I5b7c21c16e95cc1a3160e356d6e64f1f8c449e6e Signed-off-by: Oleksij Rempel <linux@rempel-privat.de> Reviewed-on: http://openocd.zylin.com/2795 Tested-by: jenkins Reviewed-by: Paul Fertser <fercerpav@gmail.com>
2015-11-13target: cortex_a: add deinit_target handler to free memoryPaul Fertser
Tested with Valgrind accesing a Pandaboard. Change-Id: I51bba044974ecfc4d418998816d44a8563264123 Signed-off-by: Paul Fertser <fercerpav@gmail.com> Reviewed-on: http://openocd.zylin.com/3101 Tested-by: jenkins Reviewed-by: Freddie Chopin <freddie.chopin@gmail.com>
2015-11-07target: cortex_a: do not create new register cache every resetPaul Fertser
Commit 68101e67ac16bdead3bd6d48cbe0a2bfd63aac02 introduced a regression which resulted for ever-growing registers list (as output by "reg" command), its contents were doubled every reset (actually, every examination). Change-Id: Ie3409c795160a2fc840a5e8a892928df0bcc0c57 Reported-by: Daniele Emancipato <daniele12457@hotmail.com> Signed-off-by: Paul Fertser <fercerpav@gmail.com> Reviewed-on: http://openocd.zylin.com/3100 Tested-by: jenkins Reviewed-by: Matthias Welwarsky <matthias@welwarsky.de> Reviewed-by: Freddie Chopin <freddie.chopin@gmail.com>
2015-11-07Cortex A/R : Allow interrupt disable during single-stepEvan Hunter
Example usage: cortex_a maskisr on cortex_a maskisr off cortex_r maskisr on cortex_r maskisr off Change-Id: I799288d9b848a06f561ba29ec1eb8e5eeace5685 Signed-off-by: Evan Hunter <ehunter@broadcom.com> Reviewed-on: http://openocd.zylin.com/2876 Tested-by: jenkins Reviewed-by: Matthias Welwarsky <matthias@welwarsky.de> Reviewed-by: Freddie Chopin <freddie.chopin@gmail.com>
2015-04-24target/cortex_a: examination should be done every time it's asked forPaul Fertser
It was observed on AM437x that after every reset the target's debug regions are unpowered. To be able to properly communicate with the target and perform cortex_a init debug access after a reset event the examination need to be performed every time, not just on OpenOCD start. Change-Id: Idf272e127ee88341e806ee00df154eade573451d Signed-off-by: Paul Fertser <fercerpav@gmail.com> Reviewed-on: http://openocd.zylin.com/2723 Tested-by: jenkins Reviewed-by: Felipe Balbi <balbi@ti.com>
2015-04-16Fix several format specifiers errors exposed by arm-none-eabiPaul Fertser
Change-Id: I1fe5c5c0b22cc23deedcf13ad5183c957551a1b7 Signed-off-by: Paul Fertser <fercerpav@gmail.com> Reviewed-on: http://openocd.zylin.com/2719 Tested-by: jenkins
2015-04-14target/cortex_a: emit a clear error message when dbgbase can't be detectedPaul Fertser
In some cases (the most obvious are TI's SoCs) ROM table lacks entries for the cores, so OpenOCD has no way to determine what debug base to use. Due to an error fixed in ec9ccaa28849 it wasn't handled properly, and OpenOCD would continue to try using dbgbase = 0, which happened to work for e.g. AM437x. This patch adds a clear indication to the user that to access such a target, dbgbase must be set manually in the config. Reported by Felipe Balbi on IRC. Change-Id: Id8533e708f44b76550eb8b659564f5f45717c298 Signed-off-by: Paul Fertser <fercerpav@gmail.com> Reviewed-on: http://openocd.zylin.com/2603 Tested-by: jenkins
2015-04-14Cortex-A: Don't flush the data/unified cache if MMU is offUwe Kleine-König
When the SCTLR has C set but M unset (i.e. Caching on, but MMU off) the cache if effectively off. So only flush the cache if MMU is on, otherwise stale entries might be committed to memory. Change-Id: Iaff8b6f25b7a41ba838b91d45684c98f99fc0b27 Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de> Reviewed-on: http://openocd.zylin.com/2429 Tested-by: jenkins Reviewed-by: Christopher Head <chead@zaber.com> Reviewed-by: Paul Fertser <fercerpav@gmail.com> Reviewed-by: Vladimir Svoboda <ze.vlad@gmail.com>
2015-03-09target/cortex_a: remove dead assignmentPaul Fertser
Found by clang static checker. Change-Id: I77b0dc18188328fdb28d07b9e5c52e06182d9e2b Signed-off-by: Paul Fertser <fercerpav@gmail.com> Reviewed-on: http://openocd.zylin.com/2561 Tested-by: jenkins Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
2015-02-22Cortex A: fix extra memory read and non-word sizesChristopher Head
Without this patch, to perform a memory read, OpenOCD first issues an LDC instruction into DBGITR in Stall mode (thus executing the instruction), then switches to Fast mode and reads from DBGDTRTX once for each word to transfer. At the very end of the transfer, the final Fast mode read of DBGDTRTX has, as always, the side effect of re-issuing the LDC instruction. This causes two problems: (1) If the word immediately beyond the end of the requested region is inaccessible, this spurious LDC will cause a fault. On a fast CPU, the LDC will finish executing by the time the poll of DSCR takes place, failing the entire memory read. On a slow CPU, the LDC might finish executing later, leaving an unexpected and confusing sticky fault lying around for the next operation to see. (2) If the LDC succeeds, it will leave the loaded word in DBGDTRTX, thus setting DBGDSCR.TXFULL=1. The cortex_a_read_apb_ab_memory routine completes without consuming that last word, thus confusing the next routine that tries to use DBGDTRTX (this may not have any visible effect on some implementations, because writing to DBGDTRTXint when TXFULL=1 is defined as Unpredictable, but I believe it caused a visible problem for me). With this patch, the bulk mem_ap_sel_read_buf_noincr is modified to omit the last word of the block. The second-to-last read of DBGDTRTX by that function will cause the issue of the LDC for the last word. After switching back to Normal mode and waiting for that instruction to finish, do a final read of DBGDTRTX to extract the last word into the buffer, leaving TXFULL=0. Without this patch, memory accesses are always expanded such that they are aligned to the access size. With this patch, accesses are issued exactly as ordered by the caller. The caller is expected to handle fragments at the beginning and end of the transfer if the address is unaligned and an unaligned access is not desired. Without this patch, the DFAR and DFSR registers, which report the location and status of data faults, are ignored while performing memory accesses, which could cause problems debugging an OS page fault handler. With this patch, DFAR and DFSR are preserved across memory accesses, and DFSR is decoded in the event of a synchronous fault to provide the caller with more information about the reason for failure. Thanks to Boris Brezillon for the original patch whose ideas led to the non-word access mechanism implemented here and to various code reviewers for their comments. Change-Id: I11ae7104fbe69a522efadefc705c9a217a7eef41 Signed-off-by: Christopher Head <chead@zaber.com> Reviewed-on: http://openocd.zylin.com/2381 Tested-by: jenkins Reviewed-by: Olivier Schonken <olivier.schonken@gmail.com> Reviewed-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>
2015-02-11cortex_a: Add Cortex-A5 identificationOlivier Schonken
Add Cortex-A5 identification to ROM-table display, and also to cortex_a_init_debug_access. This change is mostly cosmetic. Change-Id: I7b1dd8755d70d45eb5f315aa1918d44a813b3cdf Signed-off-by: Olivier Schonken <olivier.schonken@gmail.com> Reviewed-on: http://openocd.zylin.com/2483 Tested-by: jenkins Reviewed-by: Paul Fertser <fercerpav@gmail.com>
2015-01-10cortex_a: Add support for A7 MPCoreAlexander Stein
A7 MPCore needs unlocking the debug registers same as with A15 MPCore. Found out by hacking on the code. Change-Id: I613cb4fb35007b85b4a9a401577b47768bc1a08b Signed-off-by: Alexander Stein <alexander.stein@systec-electronic.com> Reviewed-on: http://openocd.zylin.com/2344 Tested-by: jenkins Reviewed-by: Kamal Dasu <kamal.dasu@gmail.com> Reviewed-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>
2015-01-10cortex_a: Add support for A15 MPCoreKamal Dasu
Added Cortex-A15 support for DAP AHB-AP init code as per ADI V5 spec. Also added changes to make the APB MEM-AP to work with A15. Made the the cortex_a target code generic to work with A8, A9 and A15 single core or multicore implementation. Added armv7a code for os_border calculation to work for known A8, A9 and A15 platforms based on the ARM DDI 0344H, ARM DDI 0407F, ARM DDI 0406C ARMV7A architecture docs. Change-Id: Ib2803ab62588bf40f1ae4b9192b619af31525a1a Signed-off-by: Kamal Dasu <kdasu.kdev@gmail.com> Reviewed-on: http://openocd.zylin.com/1601 Tested-by: jenkins Reviewed-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>
2014-10-06arm_adi_v5: make dap_lookup_cs_component() traverse subtables and handle ↵Paul Fertser
multicore When looking for a debug base address of a core, one should search through all the ROM tables, not just the top-level one. This code also assumes that the first found entry (in a depth-first search) will correspond to core 0, the second to core 1 etc. The patch is supposed to be an alternative implementation of http://openocd.zylin.com/#/c/1313/. Change-Id: Ifc88971a02fe3d9c00d9bf72a822ade5804d4e09 Signed-off-by: Paul Fertser <fercerpav@gmail.com> Reviewed-on: http://openocd.zylin.com/1920 Tested-by: jenkins Reviewed-by: Andreas Fritiofson <andreas.fritiofson@gmail.com> Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
2014-07-03cortex_a: target implementation renames cortex_a8 to cortex_aKamal Dasu
A previous commit changes the target name used by tcl scripts. commit d9ba56c295f057e716519a798bf9cdb4898c24f4 target: rename cortex_a8 to cortex_a The current change renames target functions and definitions in the implementation from cortex_a8 to cortex_a. This prepares the implementation to support Cortex-A8, A9, A15-MPCore in one place. Change-Id: I73b5a38a92c12ba5bd3b806fbbb664817575a6d7 Signed-off-by: Kamal Dasu <kdasu.kdev@gmail.com> Reviewed-on: http://openocd.zylin.com/1599 Tested-by: jenkins Reviewed-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>
2014-06-22cortex_a: fix lockup when writing to high addressSeth LaForge
On a processor with caches, when you write data to memory OpenOCD invalidates the cache lines affected. If you write to an address within 64 bytes of UINT32_MAX, then the for loop control variable wrapped around resulting in an infinite loop. Change control variable to be an offset from the address involved. We should never be asked to write 2^32 bytes, so wraparound should not be a problem. Change-Id: Ibfe654113eff71684862ff651e7a1cd05ccc6760 Signed-off-by: Seth LaForge <sethml@google.com> Reviewed-on: http://openocd.zylin.com/2126 Tested-by: jenkins Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
2014-04-14target/cortex_a: check gdb_service before dereferencing in update_halt_gdbPaul Fertser
If gdb was disconnected by the moment the target entered halted state, update_halt_gdb would segfault. Change-Id: I67477e9199c1df097be83a49e38602f975c083f5 Reported-by: Younes REGAIEG <younes.regaieg@imag.fr> Signed-off-by: Paul Fertser <fercerpav@gmail.com> Reviewed-on: http://openocd.zylin.com/2098 Tested-by: jenkins Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
2014-03-07cortex_a: Fix endianess issues in cortex_a8_*_apb_ab_memoryKamal Dasu
Make the APB-AB memory read routines handle endianess order when running on big endian host. cortex_a8_read_apb_ab_memory is also called by cortex_a8_write_apb_ab_memory and was breaking both APB-AB read and write functions. Also fixed bug in write function in calculating the offset of end of buffer data. The change aslo fixes the read issues with all combinations of aligned unaligned memory access found by 'test_mem_access' cmd. Tested with target "test_mem_access 4000", also size 1-9, 'mdb/h/w' 'mwb/h/w' cmds and equivalent gdb 'x' 'set' cmds. Change-Id: Ia927c60c4837617f5342a9beb6fdab1f061855fe Signed-off-by: Kamal Dasu <kdasu.kdev@gmail.com> Reviewed-on: http://openocd.zylin.com/1781 Reviewed-by: Andreas Fritiofson <andreas.fritiofson@gmail.com> Tested-by: jenkins
2014-02-06cortex_a: do not try to use MMU for translation if it wasn't enabled on ↵Paul Fertser
target stop On a target where AHB AP memory access is unavailable, care should be taken to avoid treating addresses as virtual if the MMU was disabled at the time the target was stopped. Without this it's impossible to peek memory with Gdb when debugging e.g. a bootloader because cortex_a8_read_memory() unconditionally tried (and failed because of a sanity check in cortex_a8_mmu_modify) to enable MMU. Change-Id: Id7c63f4912920fb71a6104226ec6428d18c96a56 Reported-by: mbm@openwrt.org Signed-off-by: Paul Fertser <fercerpav@gmail.com> Reviewed-on: http://openocd.zylin.com/1787 Tested-by: jenkins Reviewed-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>
2014-01-11adi_v5: Remove unnecessary MEM-AP access functionsAndreas Fritiofson
It's far nicer to pass a size parameter than to split the calls to separate wrappers which are combined to a single function anyway. Change-Id: I716741ebf916f6f8e9358a31c8f4fe761107c82f Signed-off-by: Andreas Fritiofson <andreas.fritiofson@gmail.com> Reviewed-on: http://openocd.zylin.com/1847 Tested-by: jenkins Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
2013-10-31Clean up many C99 integer types format specifiersPaul Fertser
This eliminates most of the warnings reported when building for arm-none-eabi (newlib). Hsiangkai, there're many similar warnings left in your nds32 files, I didn't have the nerve to clean them all, probably you could pick it up. Change-Id: Id3bbe2ed2e3f1396290e55bea4c45068165a4810 Signed-off-by: Paul Fertser <fercerpav@gmail.com> Reviewed-on: http://openocd.zylin.com/1674 Tested-by: jenkins Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
2013-09-08target: remove unimplemented target_request_data implementationsSpencer Oliver
Change-Id: Ia9afa83752d17f0f56bdf3bd81f5c69d108aa5e9 Signed-off-by: Spencer Oliver <spen@spen-soft.co.uk> Reviewed-on: http://openocd.zylin.com/1537 Tested-by: jenkins Reviewed-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>
2013-09-08target: remove unimplemented soft_reset_halt implementationsSpencer Oliver
Let the default handler issue an unsupported warning rather than using empty handler routines that may/may not issue a unsupported warning. Change-Id: Iafe3e45146981a4cfae39771c3ab7370ac86da48 Signed-off-by: Spencer Oliver <spen@spen-soft.co.uk> Reviewed-on: http://openocd.zylin.com/1535 Tested-by: jenkins Reviewed-by: Andreas Fritiofson <andreas.fritiofson@gmail.com> Reviewed-by: Hsiangkai Wang <hsiangkai@gmail.com>
2013-06-12cortex_a: remove memory leak on failureSpencer Oliver
If mem_ap_sel_write_atomic_u32 fails then tmp_buff may not be released. Detected by clang. Change-Id: I3d5416bd47d0eea61f61ec02ac5e43c82f114108 Signed-off-by: Spencer Oliver <spen@spen-soft.co.uk> Reviewed-on: http://openocd.zylin.com/1433 Tested-by: jenkins Reviewed-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>
2013-06-05update files to correct FSF addressSpencer Oliver
Change-Id: I429f7fd51f77b0e7c86d7a7f110ca31afd76c173 Signed-off-by: Spencer Oliver <spen@spen-soft.co.uk> Reviewed-on: http://openocd.zylin.com/1426 Tested-by: jenkins Reviewed-by: Paul Fertser <fercerpav@gmail.com>
2013-06-03cortex_a: fix FTBS on ARM due to alignment issuesAndreas Fritiofson
Native compilation on RaspberryPi with gcc (Debian 4.6.3-1) 4.6.3 Target: arm-linux-gnueabi ends with error: cortex_a.c: In function 'cortex_a8_read_apb_ab_memory': cortex_a.c:2063:40: error: cast increases required alignment of target type [-Werror=cast-align] cc1: all warnings being treated as errors Also check for malloc failure. This patch is compile-tested only. Change-Id: I580c505424d03ac3a565de54182db22277c52ac1 Signed-off-by: Andreas Fritiofson <andreas.fritiofson@gmail.com> Reviewed-on: http://openocd.zylin.com/1369 Tested-by: jenkins Reviewed-by: Freddie Chopin <freddie.chopin@gmail.com> Reviewed-by: Paul Fertser <fercerpav@gmail.com> Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
2013-05-28targets: fix target_type name for Cortex-A targetsPaul Fertser
Commit d9ba56c295f057e716519a798bf9cdb4898c24f4 did a bunch of renaming of cortex_a8 to cortex_a, including the names in config files. However that introduced a regression as the name in target_type struct remained unchanged. This adds the last missing bit: actual renaming of the target name as understood by OpenOCD. Also change the (hopefully) last instance of using it in the supplied config files, namely from imx6.cfg. Change-Id: Ib9289fc6d946630133ec6e36c20015ccb50acf61 Signed-off-by: Paul Fertser <fercerpav@gmail.com> Reviewed-on: http://openocd.zylin.com/1420 Tested-by: jenkins Reviewed-by: Chris Johns <chrisj@rtems.org> Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
2013-04-28target: rename cortex_a8 to cortex_aSpencer Oliver
Rename cortex_a8 target to use a more correct cortex_a name. This also adds a deprecated_name var so that older scripts issue a warning to update the target name. cfg files have also been updated to the new target name. Change-Id: I0eb1429c9281321efeb444b27a662a941a2ab67f Signed-off-by: Spencer Oliver <spen@spen-soft.co.uk> Reviewed-on: http://openocd.zylin.com/1130 Tested-by: jenkins Reviewed-by: Freddie Chopin <freddie.chopin@gmail.com>
2013-03-15target: fix broken Cortex-R4 supportSpencer Oliver
This regression was caused due to the recent addition of R4 support and the removal of the bulk_write_memory handler. Change-Id: Ide692737f235c0e9906becb6f3502ba52c5907aa Signed-off-by: Spencer Oliver <spen@spen-soft.co.uk> Reviewed-on: http://openocd.zylin.com/1246 Tested-by: jenkins
2013-03-15target: Add default implementation of bulk_write_memoryAndreas Fritiofson
Remove dummy implementations from all targets except arm7_9 and mips, which are the only ones with real implementations. Replace with a single default implementation simply calling target_write_memory(). Change-Id: I9228104240bc0b50661be20bc7909713ccda2164 Signed-off-by: Andreas Fritiofson <andreas.fritiofson@gmail.com> Reviewed-on: http://openocd.zylin.com/1213 Tested-by: jenkins Reviewed-by: Øyvind Harboe <oyvindharboe@gmail.com> Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
2013-03-15arch: Added ARMv7R and Cortex-R4 supportEvan Hunter
Rewrite to merge Cortex-A and Cortex-R code Change-Id: I4541557980d43d1bba6e8d1bfeb04f536ed25a00 Signed-off-by: Evan Hunter <ehunter@broadcom.com> Reviewed-on: http://openocd.zylin.com/358 Tested-by: jenkins Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
2013-03-15adi_v5: search for Debug and Memory AP supportEvan Hunter
Adds dap_find_ap() function. Change-Id: I6643025624009b12d4936de67a605da52c07be49 Signed-off-by: Evan Hunter <ehunter@broadcom.com> Reviewed-on: http://openocd.zylin.com/909 Tested-by: jenkins Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
2013-03-15cortex_a : optimize apb read/write access.Evan Hunter
Rewrite: Adheres more closely to 'fast read/write' examples in TRM. up to 50x faster Change-Id: Ieb4da57d8367628f3e7306827a5b1f0ab550e641 Signed-off-by: Evan Hunter <ehunter@broadcom.com> Reviewed-on: http://openocd.zylin.com/903 Tested-by: jenkins Reviewed-by: Michel JAOUEN <michel.jaouen@stericsson.com> Reviewed-by: Freddie Chopin <freddie.chopin@gmail.com> Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
2013-03-13target: Remove read_memory_impAndreas Fritiofson
Change-Id: Idc6ef3b075ccbb5945df8fea746011cb17175d8f Signed-off-by: Andreas Fritiofson <andreas.fritiofson@gmail.com> Reviewed-on: http://openocd.zylin.com/1219 Tested-by: jenkins Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
2013-03-13target: Remove write_memory_impAndreas Fritiofson
Change-Id: I5d933bc19443bba8a0193c90471fdd0614324a92 Signed-off-by: Andreas Fritiofson <andreas.fritiofson@gmail.com> Reviewed-on: http://openocd.zylin.com/1218 Tested-by: jenkins Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
2012-12-09cortex_a: Fix target entry state route.Evan Hunter
If target is disabled at init, then is examined using 'arp_examine', it can get to cortex_a8_poll with the target state being unknown. Change-Id: Ifffb345bf971d275d2eb1912648b29f0a75f6ccc Signed-off-by: Evan Hunter <ehunter@broadcom.com> Reviewed-on: http://openocd.zylin.com/954 Tested-by: jenkins Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
2012-05-28build: remove src file execute permissionSpencer Oliver
Change-Id: I42a250cdfcd03424a63cd1a255f9cf4a3c6e3ccd Signed-off-by: Spencer Oliver <spen@spen-soft.co.uk> Reviewed-on: http://openocd.zylin.com/671 Reviewed-by: Xiaofan <xiaofanc@gmail.com>
2012-02-06build: cleanup src/target directorySpencer Oliver
Change-Id: Ia055b6d2b5f6449a38afd0539a8c66e7d7e0c059 Signed-off-by: Spencer Oliver <spen@spen-soft.co.uk> Reviewed-on: http://openocd.zylin.com/430 Tested-by: jenkins
2012-01-23cleanup: rename armv4_5 to arm for readabilitySpencer Oliver
Nothing more than a name change, just to make reading the code a bit simpler. Change-Id: I73a16b7302b48ce07d9688162955aae71d11eb45 Signed-off-by: Spencer Oliver <spen@spen-soft.co.uk> Reviewed-on: http://openocd.zylin.com/390 Tested-by: jenkins Reviewed-by: Øyvind Harboe <oyvindharboe@gmail.com>
2012-01-18cmd: add missing usage varsSpencer Oliver
we should have caught them all - hopefully. Change-Id: I35435317fccaf5ad0216244d69f76db6857bb582 Signed-off-by: Spencer Oliver <spen@spen-soft.co.uk> Reviewed-on: http://openocd.zylin.com/381 Tested-by: jenkins Reviewed-by: Øyvind Harboe <oyvindharboe@gmail.com>
generated by cgit v1.2.3-18-g5258 (git 2.32.0) at 2024-10-17 18:45:03 +0000