diff options
| author | Matthias Welwarsky <matthias@welwarsky.de> | 2015-10-16 09:25:25 +0200 |
|---|---|---|
| committer | Paul Fertser <fercerpav@gmail.com> | 2015-11-30 05:40:57 +0000 |
| commit | 8704e53665910ba71e5bc3f99b32ead0060e1a3e (patch) | |
| tree | 0be18ed0939e0905f1e23ef02c7fe7ebc3590da7 /src/target/cortex_a.c | |
| parent | 3a292a1f34586b265b92e4662652683645e14201 (diff) | |
armv7a: fix handling of inner caches
ARMv7 architecture allows up to 7 cache levels that are architecturally
visible, as opposed to "system caches", which are outside of the domain
defined by ARMv7 and require separate management. This patch enables
detection and identification of caches at all levels. It also implements
a new "flush-all" function that cleans & invalidates all cache levels to
the "Point of Coherence".
Change-Id: Ib77115d6044d39845907941c6f031e208f6e0aa5
Signed-off-by: Matthias Welwarsky <matthias@welwarsky.de>
Reviewed-on: http://openocd.zylin.com/3024
Reviewed-by: Paul Fertser <fercerpav@gmail.com>
Tested-by: jenkins
Diffstat (limited to 'src/target/cortex_a.c')
| -rw-r--r-- | src/target/cortex_a.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/target/cortex_a.c b/src/target/cortex_a.c index 5fd87318..f9c92736 100644 --- a/src/target/cortex_a.c +++ b/src/target/cortex_a.c @@ -1305,7 +1305,7 @@ static int cortex_a_post_debug_entry(struct target *target) LOG_DEBUG("cp15_control_reg: %8.8" PRIx32, cortex_a->cp15_control_reg); cortex_a->cp15_control_reg_curr = cortex_a->cp15_control_reg; - if (armv7a->armv7a_mmu.armv7a_cache.ctype == -1) + if (armv7a->armv7a_mmu.armv7a_cache.info == -1) armv7a_identify_cache(target); if (armv7a->is_armv7r) { |