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2017-02-10aarch64: unify armv7-a and armv8 debug entry decodingMatthias Welwarsky
Make DSCR_RUN_MODE() usable for armv8 and arm7 debug Change-Id: Ib3ba3000d5b6aa03e590f3ca4969e677474eb12c Signed-off-by: Matthias Welwarsky <matthias.welwarsky@sysgo.com>
2017-02-10arm_dpm: Add new state ARM_STATE_AARCH64David Ung
Add new enum ARM_STATE_AARCH64 to the list of possible states. Change-Id: I3cb2df70f8d5803a63d8374bf3eb75de988e24f8 Signed-off-by: David Ung <david.ung.42@gmail.com> Signed-off-by: Matthias Welwarsky <matthias.welwarsky@sysgo.com>
2017-02-10target: Add 64-bit target address supportDongxue Zhang
Define a target_addr_t type to support 32-bit and 64-bit addresses at the same time. Also define matching TARGET_PRI*ADDR format macros as well as a convenient TARGET_ADDR_FMT. In targets that are 32-bit (avr32, nds32, arm7/9/11, fm4, xmc1000) be least invasive by leaving the formatting unchanged apart from the type; for generic code adopt TARGET_ADDR_FMT as unified address format. Don't silently change gdb formatting here, leave that to later. Add COMMAND_PARSE_ADDRESS() macro to abstract the address type. Implement it using its own parse_target_addr() function, in the hopes of catching pointer type mismatches better. Add '--disable-target64' configure option to revert to previous 32-bit target address behavior. Change-Id: I2e91d205862ceb14f94b3e72a7e99ee0373a85d5 Signed-off-by: Dongxue Zhang <elta.era@gmail.com> Signed-off-by: David Ung <david.ung.42@gmail.com> [AF: Default to enabling (Paul Fertser), rename macros, simplify] Signed-off-by: Andreas Färber <afaerber@suse.de> Signed-off-by: Matthias Welwarsky <matthias.welwarsky@sysgo.com>
2016-12-25target: cortex_a: fix segfault when SPSR is not properly handledPaul Fertser
OpenOCD doesn't (yet) know how to handle HYP mode properly so spsr register is not getting initialised when OpenOCD connects to a target stopped in this mode. Reported on IRC by thinkfat and nearffxx. Change-Id: I4bda9ba0c582c8e9cacefe708cc4a3d947151f84 Signed-off-by: Paul Fertser <fercerpav@gmail.com> Reviewed-on: http://openocd.zylin.com/3906 Tested-by: jenkins Reviewed-by: Matthias Welwarsky <matthias@welwarsky.de> Reviewed-by: Chengyu Zheng <chengyu.zheng@polimi.it>
2016-12-08cortex_a: fix reset for SWD transportMatthias Welwarsky
Change b0698501b0e789091e9f9f1427b32af304888769 fixed reset for i.MX6 and TI Sitara SoCs but broke reset for cortex-a targets that use SWD. This patch is a work- around that forces asserting SRST when SWD is used. Change-Id: I7e39f2a469b9b4b2b74ad48ba49f2eeb58528921 Signed-off-by: Matthias Welwarsky <matthias.welwarsky@sysgo.com> Reviewed-on: http://openocd.zylin.com/3641 Tested-by: jenkins Reviewed-by: Paul Fertser <fercerpav@gmail.com>
2016-12-08semihosting: support fileio operationSteven Stallion
This patch adds support for bridging semihosting to GDB's File-I/O remote protocol extension. For the most part operations match up 1:1, however some require a working area to complete successfully, namely operations that devolve to read, stat, and gettimeofday. A new command was added to enable support for fileio named `arm semihosting_fileio`, which ensures that the default behavior remains intact for those that prefer it. Finally, redundant logging was removed from the target_arch_state function; this permits ARM targets to quiesce log output when polling for a fileio reply. This prevents filling the logs with halt/resume messages when using semihosting fileio. Change-Id: Ifbb864fc2373336a501cc0332675b887b552e1ee Signed-off-by: Steven Stallion <stallion@squareup.com> Reviewed-on: http://openocd.zylin.com/3566 Tested-by: jenkins Reviewed-by: Steven Stallion <sstallion@gmail.com> Reviewed-by: Paul Fertser <fercerpav@gmail.com>
2016-12-08Cortex-R: Force usage of physical memory read/write since there is no MMUEvan Hunter
Change-Id: I69d6e6301ab66744258fe650a76c7241bebe00a8 Signed-off-by: Evan Hunter <ehunter@broadcom.com> Reviewed-on: http://openocd.zylin.com/3203 Tested-by: jenkins Reviewed-by: Girts Folkmanis <opensource@girts.me> Reviewed-by: Matthias Welwarsky <matthias@welwarsky.de> Reviewed-by: Jiri Kastner <cz172638@gmail.com> Reviewed-by: Paul Fertser <fercerpav@gmail.com>
2016-12-08cortex_a: remove partnum magic from arp_examine and dbginitMatthias Welwarsky
Depending on the Debug implementation the "OS Lock" feature might be implemented or not. It is not actually depending on the part number of the implemented ARM core but on the DBGOSLSR.OSLM bits. This patch removes querying the part number and implements proper parsing of OSLM. Result is a more generic approach that will work out-of-box on more devices. Change-Id: I79e052869c2f9af1d7fdedef42faddb7292e7332 Signed-off-by: Matthias Welwarsky <matthias@welwarsky.de> Reviewed-on: http://openocd.zylin.com/3213 Tested-by: jenkins Reviewed-by: Paul Fertser <fercerpav@gmail.com>
2016-11-04cortex_a/r/m: fix handling of un-examined coresMatthias Welwarsky
On multi-core systems, with some cores in power-down state, examination will fail for these cores. Make sure assert- and deassert_reset functions don't crash due to uninitialized variables. Change-Id: I472f8d19af2cd3c770c05f3e57a31b35a863b687 Signed-off-by: Matthias Welwarsky <matthias.welwarsky@sysgo.com> Reviewed-on: http://openocd.zylin.com/3552 Tested-by: jenkins Reviewed-by: Jiri Kastner <cz172638@gmail.com> Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
2016-11-04semihosting armv7a: Add support for ARMv7-AAndrey Smirnov
Add semihosting support for ARMv7-A based processors. Tested with custom Vybrid VF610 based board and Pandaboard ES (Rev. B1) board (Cortex-A9). Change-Id: I6b896a61c1c6a1c5dcf89de834486f82dd6c80a2 Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com> Signed-off-by: Tsung-Han Lin <tsunghan.tw@gmail.com> Reviewed-on: http://openocd.zylin.com/2908 Reviewed-by: Andreas Fritiofson <andreas.fritiofson@gmail.com> Tested-by: jenkins
2016-05-24Remove FSF address from GPL noticesMarc Schink
Also make GPL notices consistent according to: https://www.gnu.org/licenses/gpl-howto.html Change-Id: I84c9df40a774958a7ed91460c5d931cfab9f45ba Signed-off-by: Marc Schink <openocd-dev@marcschink.de> Reviewed-on: http://openocd.zylin.com/3488 Tested-by: jenkins Reviewed-by: Andreas Färber <afaerber@suse.de> Reviewed-by: Freddie Chopin <freddie.chopin@gmail.com> Reviewed-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>
2016-05-20Fix spelling of ARM CortexAndreas Färber
It's Cortex-Xn, not Cortex Xn or cortex xn or cortex-xn or CORTEX-Xn or CortexXn. Further it's Cortex-M0+, not M0plus. Cf. http://www.arm.com/products/processors/index.php Consistently write it the official way, so that it stops propagating. Originally spotted in the documentation, it mainly affects code comments but also Atmel SAM3/SAM4/SAMV, NiietCM4 and SiM3x flash driver output. Found via: git grep -i "Cortex " git grep -i "Cortex-" | grep -v "Cortex-" | grep -v ".cpu" git grep -i "CortexM" Change-Id: Ic7b6ca85253e027f6f0f751c628d1a2a391fe914 Signed-off-by: Andreas Färber <afaerber@suse.de> Reviewed-on: http://openocd.zylin.com/3483 Tested-by: jenkins Reviewed-by: Marc Schink <openocd-dev@marcschink.de> Reviewed-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>
2016-05-20cortex_a: Rename APB-AP to CPU in memory contextsAndreas Fritiofson
Memory accesses are not made through the APB-AP, they are made through the CPU (which happens to be controlled over the APB-AP). Rename all irrelevant uses of the APB-AP term. And fix the long standing typo in the function names... Change-Id: Ide466fb2728930968bdba698f0dd9012cc9dbdf9 Signed-off-by: Andreas Fritiofson <andreas.fritiofson@gmail.com> Reviewed-on: http://openocd.zylin.com/3216 Tested-by: jenkins Reviewed-by: Andreas Färber <afaerber@suse.de> Reviewed-by: Freddie Chopin <freddie.chopin@gmail.com>
2016-05-08cortex_a: fix cortex_a_assert_reset() if srst_gates_jtagMatthias Welwarsky
The cortex_a specific assert_reset function must only apply nSRST if the reset configuration states that JTAG can be used while nSRST is asserted. Change-Id: If604a65fdea5bcb46ec723ada547a4e8d6fa8c59 Signed-off-by: Matthias Welwarsky <matthias.welwarsky@sysgo.com> Reviewed-on: http://openocd.zylin.com/3356 Tested-by: jenkins Reviewed-by: Freddie Chopin <freddie.chopin@gmail.com>
2016-05-05target: improve robustness of reset commandTomas Vanek
Before this change jim_target_reset() checked examined state of a target and failed without calling .assert_reset in particular target layer (and without comprehensible warning to user). Cortex-M target (which refuses access to DP under active SRST): If connection is lost then reset process fails before asserting SRST and connection with MCU is not restored. This resulted in: 1) A lot of Cortex-M MCUs required use of reset button or cycling power after firmware blocked SWD access somehow (sleep, misconfigured clock etc). If firmware blocks SWD access early during initialization, a MCU could become completely inaccessible by SWD. 2) If OpenOCD is (re)started and a MCU is in a broken state unresponsive to SWD, reset command does not work even if it could help to restore communication. Hopefully this scenario is not possible under full JTAG. jim_target_reset() in target.c now does not check examined state and delegates this task to a particular target. All targets have been checked and xx_assert_reset() (or xx_deassert_reset()) procedures were changed to check examined state if needed. Targets except arm11, cortex_a and cortex_m just fail if target is not examined although it may be possible to use at least hw reset. Left as TODO for developers familiar with these targets. cortex_m_assert_reset(): memory access errors are stored instead of immediate returning them to a higher level. Errors from less important reads/writes are ignored. Requested reset always leads to a configured action. arm11_assert_reset() just asserts hw reset in case of not examined target. cortex_a_assert_reset() works as usual in case of not examined target. Change-Id: I84fa869f4f58e2fa83b6ea75de84440d9dc3d929 Signed-off-by: Tomas Vanek <vanekt@fbl.cz> Reviewed-on: http://openocd.zylin.com/2606 Tested-by: jenkins Reviewed-by: Matthias Welwarsky <matthias@welwarsky.de> Reviewed-by: Paul Fertser <fercerpav@gmail.com>
2016-03-24cortex_a: allow physical memory access through AHB-AP againMatthias Welwarsky
This feature is required for boards that use a programmatical way to reset the cpu, like the TI Pandaboard with OMAP4. The board only has a 14 pin JTAG header that doesn't feature SRST and is reset by direct write to the PRM_RSTCTL register. iMX6 can be reset through triggering the on-chip watchdog, but for these methods to work reliably, access through the AHB-AP without interaction with the CPU core is necessary. Change-Id: I9a07a536adda83cc2f93e504384c8c7f0306220b Signed-off-by: Matthias Welwarsky <matthias.welwarsky@sysgo.com> Reviewed-on: http://openocd.zylin.com/3359 Tested-by: jenkins Reviewed-by: Paul Fertser <fercerpav@gmail.com>
2016-02-29Cortex-A/R: Fix Mask-ISR parsingEvan Hunter
Remove needless error when not halted with wrong return. Allow usage in any mode Add error message for incorrect arguments Change-Id: I3e94e159609351e503ed3f35760503079e3aa53c Signed-off-by: Evan Hunter <ehunter@broadcom.com> Reviewed-on: http://openocd.zylin.com/3195 Tested-by: jenkins Reviewed-by: Matthias Welwarsky <matthias@welwarsky.de> Reviewed-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>
2016-02-29Cortex-A/R: Add missing timeout for loop polling DSCR & fix timeout typesEvan Hunter
Change-Id: I345658cfdc8a34a98418727423ac6bd562e980f3 Signed-off-by: Evan Hunter <ehunter@broadcom.com> Reviewed-on: http://openocd.zylin.com/3201 Tested-by: jenkins Reviewed-by: Matthias Welwarsky <matthias@welwarsky.de> Reviewed-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>
2016-01-12Cortex-A: Fix unicode quote in commentEvan Hunter
Change-Id: I4747c113ab6c02199f078d9b4a4ec372d011fb2d Signed-off-by: Evan Hunter <ehunter@broadcom.com> Reviewed-on: http://openocd.zylin.com/3200 Tested-by: jenkins Reviewed-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>
2015-12-29cortex_a: add 'dacrfixup' to cortex-a command groupMatthias Welwarsky
work around issues with software breakpoints when the text segment is mapped read-only by the OS. Set DACR to "all-manager" to bypass TLB permission checks on memory access. Change-Id: I79fd9b32b04a4d538d489896470ee30b26b72b30 Signed-off-by: Matthias Welwarsky <matthias@welwarsky.de> Reviewed-on: http://openocd.zylin.com/3107 Tested-by: jenkins Reviewed-by: Paul Fertser <fercerpav@gmail.com>
2015-12-29cortex_a: select APB-AP as the default APMatthias Welwarsky
Debug initialization blindly selects AP#0 as default, which is the AHB-AP in many cases. This sets the default for target_read/write functions. However, AHB-AP is the wrong choice, because it bypasses caches on read and write and also makes some peripherals inaccessible (e.g. l2 outer caches). This patch explicitely selects the APB-AP (debug_ap) as the default. Change-Id: I13f9e0750186d35dcfc135c8d67d437c5884d9c4 Signed-off-by: Matthias Welwarsky <matthias@welwarsky.de> Reviewed-on: http://openocd.zylin.com/3113 Tested-by: jenkins Reviewed-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>
2015-12-29cortex: Set default memaccess_tck only during examineAndreas Fritiofson
It's currently set during target creation but the AP that will be used for the target is not even known. Change-Id: I4502e7eb1fa8d90f746445b8cf8a4c21cb7d519e Signed-off-by: Andreas Fritiofson <andreas.fritiofson@gmail.com> Reviewed-on: http://openocd.zylin.com/3155 Tested-by: jenkins Reviewed-by: Matthias Welwarsky <matthias@welwarsky.de>
2015-12-29arm_adi_v5: Remove all mem_ap_sel_* functionsAndreas Fritiofson
All mem_ap_* functions now make sure the SELECT register is updated with the AP number that it's operating on. This shouldn't have to be handled explicitly. Change-Id: Ib193d8930fabb6a25715064355f98258c9580b5d Signed-off-by: Andreas Fritiofson <andreas.fritiofson@gmail.com> Reviewed-on: http://openocd.zylin.com/3153 Tested-by: jenkins Reviewed-by: Matthias Welwarsky <matthias@welwarsky.de>
2015-12-29arm_adi_v5: Split ahbap_debugport_initAndreas Fritiofson
This function does two separate things, powering up the DP and setting up a MEM-AP. But the DP needs to be powered before even searching for a MEM-AP to initialize and targets may have multiple MEM-APs that need initializing. Split the function into dap_dp_init() and mem_ap_init() and change all call sites to use the appropriate one. Change-Id: I92f55e09754a93f3f01dd8e5aa1ffdf60c856126 Signed-off-by: Andreas Fritiofson <andreas.fritiofson@gmail.com> Reviewed-on: http://openocd.zylin.com/3151 Tested-by: jenkins Reviewed-by: Matthias Welwarsky <matthias@welwarsky.de>
2015-12-29arm_adi_v5: Change mem_ap calls to take pointer to AP and not DAPAndreas Fritiofson
Change-Id: I8d3e42056aa5828cb917ca578a54b7d53846a150 Signed-off-by: Andreas Fritiofson <andreas.fritiofson@gmail.com> Reviewed-on: http://openocd.zylin.com/3149 Tested-by: jenkins Reviewed-by: Matthias Welwarsky <matthias@welwarsky.de>
2015-12-29cortex_a: Find debug base using the detected APB-AP and not AP 1Andreas Fritiofson
Change-Id: I6b98c3b4486903029e5a0d6d964bd5c48ff55926 Signed-off-by: Andreas Fritiofson <andreas.fritiofson@gmail.com> Reviewed-on: http://openocd.zylin.com/3148 Tested-by: jenkins Reviewed-by: Matthias Welwarsky <matthias@welwarsky.de>
2015-12-29arm_adi_v5: Convert the AP references from numbers to pointersAndreas Fritiofson
Change the debug_ap and memory_ap fields of the cortex_a target and the debug_ap field of the cortex_m target to be pointers to the struct adiv5_ap instead of AP numbers in some known DAP. This reduces the dependency on the DAP struct in the targets and enables MEM-AP accesses to take the relevant AP as parameter. Change-Id: I39d7b134d78000564b7eec5bff464adf0ef89147 Signed-off-by: Andreas Fritiofson <andreas.fritiofson@gmail.com> Reviewed-on: http://openocd.zylin.com/3147 Tested-by: jenkins Reviewed-by: Matthias Welwarsky <matthias@welwarsky.de>
2015-12-29cortex_a: Call ahbap_debugport_init on the discovered AP and not 0Andreas Fritiofson
Change-Id: I76bb9bd800697776a375ab803402780c3c7bea35 Signed-off-by: Andreas Fritiofson <andreas.fritiofson@gmail.com> Reviewed-on: http://openocd.zylin.com/3145 Tested-by: jenkins Reviewed-by: Matthias Welwarsky <matthias@welwarsky.de>
2015-12-29target/arm: Remove usage of struct arm_jtag in ARMv7 targetsAndreas Fritiofson
The Cortex-A and Cortex-M keeps an arm_jtag struct around just to be able to pass a pointer to it to one common JTAG function which anyway only uses the TAP field. Refactor the function to take a TAP directly, remove the legacy struct from cortex instances and store the TAP pointer only in the DAP. Cortex-M makes a call to arm_jtag_setup_connection() with the struct but the function does nothing useful for a Cortex-M target so remove the call. Change-Id: I3b33709ef55372ef14522ed4337e9f2e817ae3ab Signed-off-by: Andreas Fritiofson <andreas.fritiofson@gmail.com> Reviewed-on: http://openocd.zylin.com/3142 Tested-by: jenkins Reviewed-by: Matthias Welwarsky <matthias@welwarsky.de>
2015-12-29arm_debug: Support multiple APs per DAP and remove DAP from armv7* structsPatrick Stewart
Separate out the values from adiv5_dap that are associated with a specific AP into a new struct, so we can properly support multiple APs. Remove the DAP struct from the armv7* structs, because we can have multiple CPUs per DAP, and we shouldn't have multiple DAP structs. Tidy up a few places where ap_current is used incorrectly. Change-Id: I0c6ef4b49cc86b140366347aaf9b76c07cbab0a8 Signed-off-by: Patrick Stewart <patstew@gmail.com> Reviewed-on: http://openocd.zylin.com/2984 Tested-by: jenkins Reviewed-by: Matthias Welwarsky <matthias@welwarsky.de> Reviewed-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>
2015-12-29cortex_m: Select an AP when accessing the DAPPatrick Stewart
Prepare to support multiple cortex-m cores on one DAP. Uses mem_ap_sel_* functions and removes mem_ap_* functions. Adds a new debug_ap parameter to the cortex_m (currently set to zero as in existing code). Change-Id: I6926029d1e7bf44a42d453d1aff349bda824ba72 Signed-off-by: Patrick Stewart <patstew@gmail.com> Reviewed-on: http://openocd.zylin.com/2983 Tested-by: jenkins Reviewed-by: Matthias Welwarsky <matthias@welwarsky.de> Reviewed-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>
2015-12-29cortex-a: Fix "Detected core" number is always '0'Alamy Liu
Problem No matter what target->coreid is, it always shows Detected core 0 dbgbase: ... In dap_lookup_cs_component(), it decreases the core index value to zero in order to find the desired core. The reference to coreidx is necessary considering "a device which has nested ROM tables, with each core described in its own table." (by Paul Fertser). Change-Id: I9b56d45d6edf6639e748a625ab27787f8e5a5776 Signed-off-by: Alamy Liu <alamy.liu@gmail.com> Reviewed-on: http://openocd.zylin.com/2902 Tested-by: jenkins Reviewed-by: Matthias Welwarsky <matthias@welwarsky.de> Reviewed-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>
2015-12-01cortex_a: fix fast-mode memory readsMatthias Welwarsky
cortex_a_read_apb_ab_memory_fast() uses the wrong order of ITR and DSCR writes when setting up the transfer. ARM DDI0406C says in C8.2 regarding "Fast mode" operation to first switch to fast mode and then latch the instruction in ITR. Current implementation first wrote ITR, causing the instruction to be executed immediately, then switched to fast mode without an instruction latched. Repeated reading of DTRTX didn't execute LDC and thus replicated its current content into the whole buffer. This patch uses the following, revised algorithm: 1) switch to non-blocking mode and issue the LDC for the first word 2) if more than one word is to be read: - switch to fast mode - latch the LDC instruction into ITR (it is _not_ executed) - issue (count-1) reads of DTRTX register, each read returns the current content of DTRTX and re-issues the latched instruction -> now the second-to-last word is in the buffer and the LDC for the last word has been issued. 3) wait for the last instruction to complete 4) switch back to non-blocking mode 5) Read DTRTX for the last (or: only) word and put it into the buffer Change-Id: I44f5c585962ffa5af257c3d5a2a802c122b6b1e4 Signed-off-by: Matthias Welwarsky <matthias@welwarsky.de> Reviewed-on: http://openocd.zylin.com/3122 Tested-by: jenkins Reviewed-by: Christopher Head <chead@zaber.com> Reviewed-by: Paul Fertser <fercerpav@gmail.com>
2015-11-30cortex_a: replace cortex_a_check_address functionMatthias Welwarsky
When accessing memory through the ARM core, privilege levels and mmu access permissions observed. Thus it depends on the current mode of the ARM core whether an access is possible or not. the ARM in USR mode can not access memory mapped to a higher privilege level. This means, if the ARM core is halted while executing at PL0, the debugger would be prevented from setting a breakpoint at an address with a higher privilege level, e.g. in the OS kernel. This is not desirable. cortex_a_check_address() tried to work around this by predicting if an access would fail and switched the ARM core to SVC mode. However, the prediction was based on hardcoded address ranges and only worked for Linux and a 3G/1G user/kernel space split. This patch changes the policy to always switch to SVC mode for memory accesses. It introduces two functions cortex_a_prep_memaccess() and cortex_a_post_memaccess() which bracket memory reads and writes. These function encapsulate all actions necessary for preparation and cleanup. Change-Id: I4ccdb5fd17eadeb2b66ae28caaf0ccd2d014eaa9 Signed-off-by: Matthias Welwarsky <matthias@welwarsky.de> Reviewed-on: http://openocd.zylin.com/3119 Reviewed-by: Paul Fertser <fercerpav@gmail.com> Tested-by: jenkins
2015-11-30cortex_a: rework mmu manipulationMatthias Welwarsky
when disabling the mmu to access physical addresses, normally the d-cache must be disabled as well. Disabling the d-cache also requires a full clean&invalidate. However, since all memory writes are treated as write- through no-allocate and memory reads do not allocate cache lines, effectively the d-cache state does not change at all. We can therefore save the the d-cache disabling and flushing. This patch also simplifies the function a bit. Change-Id: Ia17c56a28f432156429cd4596107e3652b788e63 Signed-off-by: Matthias Welwarsky <matthias@welwarsky.de> Reviewed-on: http://openocd.zylin.com/3114 Tested-by: jenkins Reviewed-by: Paul Fertser <fercerpav@gmail.com>
2015-11-30cortex_a: force cache and tlb bypass when cpu is in debug stateMatthias Welwarsky
for minimal impact on the hardware state, force all memory accesses to bypass the caches and tlbs. This may actually be the default, but ARM recommends in DDI0406C to set proper default values on debug init. Change-Id: If5ac097b6ee725c047b1e86c2f90eabe16b98c7b Signed-off-by: Matthias Welwarsky <matthias@welwarsky.de> Reviewed-on: http://openocd.zylin.com/3079 Reviewed-by: Paul Fertser <fercerpav@gmail.com> Tested-by: jenkins
2015-11-30cortex_a: Update instruction cache after setting a soft breakpointMatthias Welwarsky
Call armv7a_l1_d_cache_flush_virt() before writing the breakpoint, to make sure the d-cache is clean and invalid at the breakpoint location down to PoC. Call armv7a_l1_d_cache_inval_virt() after writing the breakpoint again, so that d-cache will pick up the modified code. Call armv7a_l1_i_cache_inval_virt() after writing the breakpoint to memory to make the change visible to the CPU. Change-Id: I24fc27058d99cb00d7f6002ccb623cab66b0d234 Signed-off-by: Matthias Welwarsky <matthias@welwarsky.de> Reviewed-on: http://openocd.zylin.com/3033 Reviewed-by: Paul Fertser <fercerpav@gmail.com> Tested-by: jenkins
2015-11-30armv7a: rework automatic flush-on-write handlingMatthias Welwarsky
The following changes are implemented: - Clean&Invalidate the VA range to PoC *before* the write takes place - Remove SMP handling since DCCIMVA instruction already maintains SMP coherence. - Remove separate Invalidate step Change-Id: I19fd3cc226d8ecf2937276fc63258b6a26e369a7 Signed-off-by: Matthias Welwarsky <matthias@welwarsky.de> Reviewed-on: http://openocd.zylin.com/3027 Reviewed-by: Paul Fertser <fercerpav@gmail.com> Tested-by: jenkins
2015-11-30armv7a: fix handling of inner cachesMatthias Welwarsky
ARMv7 architecture allows up to 7 cache levels that are architecturally visible, as opposed to "system caches", which are outside of the domain defined by ARMv7 and require separate management. This patch enables detection and identification of caches at all levels. It also implements a new "flush-all" function that cleans & invalidates all cache levels to the "Point of Coherence". Change-Id: Ib77115d6044d39845907941c6f031e208f6e0aa5 Signed-off-by: Matthias Welwarsky <matthias@welwarsky.de> Reviewed-on: http://openocd.zylin.com/3024 Reviewed-by: Paul Fertser <fercerpav@gmail.com> Tested-by: jenkins
2015-11-30add armv7a_cache handlersOleksij Rempel
This patch introduces, new command set and handlers for l1 and l2x caches. Patch set 10 folded the following changes into this one: Ib1a2a1fc1b929dc49532ac13a78e8eb796ab4415 If8d87a03281d0f4ad402909998e7834eb4837e79 I0749f129fa74e04f4e9c20d143a744f09ef750d8 Change-Id: I849f4d1f20610087885eeddefa81d976f77cf199 Signed-off-by: Oleksij Rempel <linux@rempel-privat.de> Signed-off-by: Matthias Welwarsky <matthias@welwarsky.de> Reviewed-on: http://openocd.zylin.com/2800 Tested-by: jenkins Reviewed-by: Paul Fertser <fercerpav@gmail.com>
2015-11-30cortex_a: add cortex_a_[read|write]_memory_ahbOleksij Rempel
Change-Id: I39c457274e1714a8d42233f7fc490fb58f5cb38e Signed-off-by: Oleksij Rempel <linux@rempel-privat.de> Reviewed-on: http://openocd.zylin.com/2798 Reviewed-by: Paul Fertser <fercerpav@gmail.com> Tested-by: jenkins
2015-11-30cortex_a: add cortex_a_[read|write]_bufferOleksij Rempel
Change-Id: I82011822d913aa7228f5c6262b540156494bedfe Signed-off-by: Oleksij Rempel <linux@rempel-privat.de> Reviewed-on: http://openocd.zylin.com/2797 Reviewed-by: Paul Fertser <fercerpav@gmail.com> Tested-by: jenkins
2015-11-30cortex_a: remove cache handlers from cortex_a_write_phys_memoryOleksij Rempel
This was needed for ahb access Change-Id: I638f45a276a593c08140b5d9d7480617aa85f096 Signed-off-by: Oleksij Rempel <linux@rempel-privat.de> Reviewed-on: http://openocd.zylin.com/2796 Reviewed-by: Paul Fertser <fercerpav@gmail.com> Tested-by: jenkins
2015-11-30cortex_a: remove ahb support for phys_memory accessOleksij Rempel
Change-Id: I5b7c21c16e95cc1a3160e356d6e64f1f8c449e6e Signed-off-by: Oleksij Rempel <linux@rempel-privat.de> Reviewed-on: http://openocd.zylin.com/2795 Tested-by: jenkins Reviewed-by: Paul Fertser <fercerpav@gmail.com>
2015-11-13target: cortex_a: add deinit_target handler to free memoryPaul Fertser
Tested with Valgrind accesing a Pandaboard. Change-Id: I51bba044974ecfc4d418998816d44a8563264123 Signed-off-by: Paul Fertser <fercerpav@gmail.com> Reviewed-on: http://openocd.zylin.com/3101 Tested-by: jenkins Reviewed-by: Freddie Chopin <freddie.chopin@gmail.com>
2015-11-07target: cortex_a: do not create new register cache every resetPaul Fertser
Commit 68101e67ac16bdead3bd6d48cbe0a2bfd63aac02 introduced a regression which resulted for ever-growing registers list (as output by "reg" command), its contents were doubled every reset (actually, every examination). Change-Id: Ie3409c795160a2fc840a5e8a892928df0bcc0c57 Reported-by: Daniele Emancipato <daniele12457@hotmail.com> Signed-off-by: Paul Fertser <fercerpav@gmail.com> Reviewed-on: http://openocd.zylin.com/3100 Tested-by: jenkins Reviewed-by: Matthias Welwarsky <matthias@welwarsky.de> Reviewed-by: Freddie Chopin <freddie.chopin@gmail.com>
2015-11-07Cortex A/R : Allow interrupt disable during single-stepEvan Hunter
Example usage: cortex_a maskisr on cortex_a maskisr off cortex_r maskisr on cortex_r maskisr off Change-Id: I799288d9b848a06f561ba29ec1eb8e5eeace5685 Signed-off-by: Evan Hunter <ehunter@broadcom.com> Reviewed-on: http://openocd.zylin.com/2876 Tested-by: jenkins Reviewed-by: Matthias Welwarsky <matthias@welwarsky.de> Reviewed-by: Freddie Chopin <freddie.chopin@gmail.com>
2015-04-24target/cortex_a: examination should be done every time it's asked forPaul Fertser
It was observed on AM437x that after every reset the target's debug regions are unpowered. To be able to properly communicate with the target and perform cortex_a init debug access after a reset event the examination need to be performed every time, not just on OpenOCD start. Change-Id: Idf272e127ee88341e806ee00df154eade573451d Signed-off-by: Paul Fertser <fercerpav@gmail.com> Reviewed-on: http://openocd.zylin.com/2723 Tested-by: jenkins Reviewed-by: Felipe Balbi <balbi@ti.com>
2015-04-16Fix several format specifiers errors exposed by arm-none-eabiPaul Fertser
Change-Id: I1fe5c5c0b22cc23deedcf13ad5183c957551a1b7 Signed-off-by: Paul Fertser <fercerpav@gmail.com> Reviewed-on: http://openocd.zylin.com/2719 Tested-by: jenkins
2015-04-14target/cortex_a: emit a clear error message when dbgbase can't be detectedPaul Fertser
In some cases (the most obvious are TI's SoCs) ROM table lacks entries for the cores, so OpenOCD has no way to determine what debug base to use. Due to an error fixed in ec9ccaa28849 it wasn't handled properly, and OpenOCD would continue to try using dbgbase = 0, which happened to work for e.g. AM437x. This patch adds a clear indication to the user that to access such a target, dbgbase must be set manually in the config. Reported by Felipe Balbi on IRC. Change-Id: Id8533e708f44b76550eb8b659564f5f45717c298 Signed-off-by: Paul Fertser <fercerpav@gmail.com> Reviewed-on: http://openocd.zylin.com/2603 Tested-by: jenkins
generated by cgit v1.2.3-18-g5258 (git 2.32.0) at 2024-10-17 10:25:40 +0000