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-rw-r--r--tcl/board/hitex_stm32-performancestick.cfg2
-rw-r--r--tcl/board/olimex_stm32_h103.cfg2
-rw-r--r--tcl/board/olimex_stm32_h107.cfg2
-rw-r--r--tcl/board/stm32100b_eval.cfg2
-rw-r--r--tcl/board/stm3210b_eval.cfg2
-rw-r--r--tcl/board/stm3210c_eval.cfg2
-rw-r--r--tcl/board/stm3210e_eval.cfg2
-rw-r--r--tcl/board/stm3220g_eval.cfg2
-rw-r--r--tcl/target/stm32f1x.cfg (renamed from tcl/target/stm32.cfg)2
-rw-r--r--tcl/target/stm32f2x.cfg (renamed from tcl/target/stm32f2xxx.cfg)2
-rw-r--r--tcl/target/stm32xl.cfg4
11 files changed, 12 insertions, 12 deletions
diff --git a/tcl/board/hitex_stm32-performancestick.cfg b/tcl/board/hitex_stm32-performancestick.cfg
index 515f7e08..0ec4076b 100644
--- a/tcl/board/hitex_stm32-performancestick.cfg
+++ b/tcl/board/hitex_stm32-performancestick.cfg
@@ -5,7 +5,7 @@ reset_config trst_and_srst
source [find interface/stm32-stick.cfg]
set CHIPNAME stm32_hitex
-source [find target/stm32.cfg]
+source [find target/stm32f1x.cfg]
# configure str750 connected to jtag chain
# FIXME -- source [find target/str750.cfg] after cleaning that up
diff --git a/tcl/board/olimex_stm32_h103.cfg b/tcl/board/olimex_stm32_h103.cfg
index 98b0b658..ec03034c 100644
--- a/tcl/board/olimex_stm32_h103.cfg
+++ b/tcl/board/olimex_stm32_h103.cfg
@@ -4,4 +4,4 @@
# Work-area size (RAM size) = 20kB for STM32F103RB device
set WORKAREASIZE 0x5000
-source [find target/stm32.cfg]
+source [find target/stm32f1x.cfg]
diff --git a/tcl/board/olimex_stm32_h107.cfg b/tcl/board/olimex_stm32_h107.cfg
index c21e19bd..1d34a234 100644
--- a/tcl/board/olimex_stm32_h107.cfg
+++ b/tcl/board/olimex_stm32_h107.cfg
@@ -5,4 +5,4 @@
# Work-area size (RAM size) = 64kB for STM32F107VC device
set WORKAREASIZE 0x10000
-source [find target/stm32.cfg]
+source [find target/stm32f1x.cfg]
diff --git a/tcl/board/stm32100b_eval.cfg b/tcl/board/stm32100b_eval.cfg
index e04b612b..41153e55 100644
--- a/tcl/board/stm32100b_eval.cfg
+++ b/tcl/board/stm32100b_eval.cfg
@@ -4,4 +4,4 @@
# The chip has only 8KB sram
set WORKAREASIZE 0x2000
-source [find target/stm32.cfg]
+source [find target/stm32f1x.cfg]
diff --git a/tcl/board/stm3210b_eval.cfg b/tcl/board/stm3210b_eval.cfg
index 70798c18..ff3f7771 100644
--- a/tcl/board/stm3210b_eval.cfg
+++ b/tcl/board/stm3210b_eval.cfg
@@ -4,4 +4,4 @@
# increase working area to 32KB for faster flash programming
set WORKAREASIZE 0x8000
-source [find target/stm32.cfg]
+source [find target/stm32f1x.cfg]
diff --git a/tcl/board/stm3210c_eval.cfg b/tcl/board/stm3210c_eval.cfg
index 27684f0d..e069c049 100644
--- a/tcl/board/stm3210c_eval.cfg
+++ b/tcl/board/stm3210c_eval.cfg
@@ -4,4 +4,4 @@
# increase working area to 32KB for faster flash programming
set WORKAREASIZE 0x8000
-source [find target/stm32.cfg]
+source [find target/stm32f1x.cfg]
diff --git a/tcl/board/stm3210e_eval.cfg b/tcl/board/stm3210e_eval.cfg
index 786d0279..91807ce3 100644
--- a/tcl/board/stm3210e_eval.cfg
+++ b/tcl/board/stm3210e_eval.cfg
@@ -4,7 +4,7 @@
# increase working area to 32KB for faster flash programming
set WORKAREASIZE 0x8000
-source [find target/stm32.cfg]
+source [find target/stm32f1x.cfg]
#
# configure FSMC Bank 1 (NOR/PSRAM Bank 2) NOR flash
diff --git a/tcl/board/stm3220g_eval.cfg b/tcl/board/stm3220g_eval.cfg
index e836f0ed..48b57c13 100644
--- a/tcl/board/stm3220g_eval.cfg
+++ b/tcl/board/stm3220g_eval.cfg
@@ -8,4 +8,4 @@ set WORKAREASIZE 0x20000
# chip name
set CHIPNAME STM32F207IGT6
-source [find target/stm32f2xxx.cfg]
+source [find target/stm32f2x.cfg]
diff --git a/tcl/target/stm32.cfg b/tcl/target/stm32f1x.cfg
index 9879c045..8007ff57 100644
--- a/tcl/target/stm32.cfg
+++ b/tcl/target/stm32f1x.cfg
@@ -68,7 +68,7 @@ $_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE
# flash size will be probed
set _FLASHNAME $_CHIPNAME.flash
-flash bank $_FLASHNAME stm32x 0x08000000 0 0 0 $_TARGETNAME
+flash bank $_FLASHNAME stm32f1x 0x08000000 0 0 0 $_TARGETNAME
# if srst is not fitted use SYSRESETREQ to
# perform a soft reset
diff --git a/tcl/target/stm32f2xxx.cfg b/tcl/target/stm32f2x.cfg
index 8a857244..b8de3843 100644
--- a/tcl/target/stm32f2xxx.cfg
+++ b/tcl/target/stm32f2x.cfg
@@ -57,5 +57,5 @@ target create $_TARGETNAME cortex_m3 -endian $_ENDIAN -chain-position $_TARGETNA
$_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE -work-area-backup 0
set _FLASHNAME $_CHIPNAME.flash
-flash bank $_FLASHNAME stm32f2xxx 0 0 0 0 $_TARGETNAME
+flash bank $_FLASHNAME stm32f2x 0 0 0 0 $_TARGETNAME
diff --git a/tcl/target/stm32xl.cfg b/tcl/target/stm32xl.cfg
index cde07df2..f72896d3 100644
--- a/tcl/target/stm32xl.cfg
+++ b/tcl/target/stm32xl.cfg
@@ -1,6 +1,6 @@
# script for stm32xl family (dual flash bank)
-source [find target/stm32.cfg]
+source [find target/stm32f1x.cfg]
# flash size will be probed
set _FLASHNAME $_CHIPNAME.flash1
-flash bank $_FLASHNAME stm32x 0x08080000 0 0 0 $_TARGETNAME
+flash bank $_FLASHNAME stm32f1x 0x08080000 0 0 0 $_TARGETNAME