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-rw-r--r--tcl/target/lpc1769.cfg17
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diff --git a/tcl/target/lpc1769.cfg b/tcl/target/lpc1769.cfg
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--- a/tcl/target/lpc1769.cfg
+++ /dev/null
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-# NXP LPC1769 Cortex-M3 with 512kB Flash and 32kB+32kB Local On-Chip SRAM,
-set CHIPNAME lpc1769
-set CPUTAPID 0x4ba00477
-set CPURAMSIZE 0x8000
-set CPUROMSIZE 0x80000
-
-# After reset the chip is clocked by the ~4MHz internal RC oscillator.
-# When board-specific code (reset-init handler or device firmware)
-# configures another oscillator and/or PLL0, set CCLK to match; if
-# you don't, then flash erase and write operations may misbehave.
-# (The ROM code doing those updates cares about core clock speed...)
-#
-# CCLK is the core clock frequency in KHz
-set CCLK 4000
-
-#Include the main configuration file.
-source [find target/lpc17xx.cfg];