diff options
| -rw-r--r-- | doc/openocd.texi | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/doc/openocd.texi b/doc/openocd.texi index f5852cc0..feb43345 100644 --- a/doc/openocd.texi +++ b/doc/openocd.texi @@ -4376,14 +4376,14 @@ The current implementation supports three JTAG TAP cores: @item @code{ls1_sap} -- this is the SAP on NXP LS102x CPUs, allowing access to physical memory addresses independently of CPU cores. @itemize @minus -@item @code{OpenCores TAP} (See: @url{http://opencores.org/project,jtag}) +@item @code{OpenCores TAP} (See: @url{http://opencores.org/project@comma{}jtag}) @item @code{Altera Virtual JTAG TAP} (See: @url{http://www.altera.com/literature/ug/ug_virtualjtag.pdf}) @item @code{Xilinx BSCAN_* virtual JTAG interface} (See: @url{http://www.xilinx.com/support/documentation/sw_manuals/xilinx14_2/spartan6_hdl.pdf}) @end itemize And two debug interfaces cores: @itemize @minus -@item @code{Advanced debug interface} (See: @url{http://opencores.org/project,adv_debug_sys}) -@item @code{SoC Debug Interface} (See: @url{http://opencores.org/project,dbg_interface}) +@item @code{Advanced debug interface} (See: @url{http://opencores.org/project@comma{}adv_debug_sys}) +@item @code{SoC Debug Interface} (See: @url{http://opencores.org/project@comma{}dbg_interface}) @end itemize @end itemize @end deffn |