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authorSpencer Oliver <spen@spen-soft.co.uk>2013-10-10 21:16:42 +0100
committerSpencer Oliver <spen@spen-soft.co.uk>2013-10-10 20:51:03 +0000
commit1c975fe30b8fb380907133462cc38a0b2e9de565 (patch)
tree435e0ccd10febade04c74ac609880b633e172ec5 /testing
parent43fc460559bb779a8867cc1eb9728e0e68fb7609 (diff)
cortex_m: target implementation renames cortex_m3 to cortex_m
We changed the actual target name quite a while ago. This changes the actual target function names/defines to also match this change. Change-Id: I4f22fb107636db2279865b45350c9c776e608a75 Signed-off-by: Spencer Oliver <spen@spen-soft.co.uk> Reviewed-on: http://openocd.zylin.com/1626 Tested-by: jenkins
Diffstat (limited to 'testing')
-rw-r--r--testing/examples/cortex/cm3-ftest.cfg8
-rw-r--r--testing/examples/cortex/fault.c18
2 files changed, 13 insertions, 13 deletions
diff --git a/testing/examples/cortex/cm3-ftest.cfg b/testing/examples/cortex/cm3-ftest.cfg
index 37937036..6f3fa5c8 100644
--- a/testing/examples/cortex/cm3-ftest.cfg
+++ b/testing/examples/cortex/cm3-ftest.cfg
@@ -15,8 +15,8 @@
# + observe fault "handling" -- loop-to-self from load_and_run (below)
#
# - Test #2: verify that "vector_catch" makes OpenOCD stops ignoring them
-# + cortex_m3 vector_catch none
-# + cortex_m3 vector_catch VECTOR
+# + cortex_m vector_catch none
+# + cortex_m vector_catch VECTOR
# + l_VECTOR (loads testcase to RAM)
# + fault triggers vector catch hardware
# + observe OpenOCD entering debug state with no assistance
@@ -31,8 +31,8 @@
proc vector_test {tag} {
halt
# REVISIT -- annoying, we'd like to scrap vector_catch output
- cortex_m3 vector_catch none
- cortex_m3 vector_catch $tag
+ cortex_m vector_catch none
+ cortex_m vector_catch $tag
eval "l_$tag"
}
diff --git a/testing/examples/cortex/fault.c b/testing/examples/cortex/fault.c
index 9a5fe194..19f2720c 100644
--- a/testing/examples/cortex/fault.c
+++ b/testing/examples/cortex/fault.c
@@ -28,7 +28,7 @@
*/
-/* These symbols match the OpenOCD "cortex_m3 vector_catch" bit names. */
+/* These symbols match the OpenOCD "cortex_m vector_catch" bit names. */
enum vc_case {
hard_err,
int_err,
@@ -71,21 +71,21 @@ int main(void)
*/
switch (VC_ID) {
- /* "cortex_m3 vector_catch hard_err" */
+ /* "cortex_m vector_catch hard_err" */
case hard_err:
/* FORCED - Fault escalation */
/* FIXME code this */
break;
- /* "cortex_m3 vector_catch int_err" */
+ /* "cortex_m vector_catch int_err" */
case int_err:
/* STKERR -- Exception stack BusFault */
/* FIXME code this */
break;
- /* "cortex_m3 vector_catch bus_err" */
+ /* "cortex_m vector_catch bus_err" */
case bus_err:
/* PRECISERR -- precise data bus read
* Here we assume a Cortex-M3 with 512 MBytes SRAM is very
@@ -97,13 +97,13 @@ int main(void)
);
break;
- /* "cortex_m3 vector_catch state_err" */
+ /* "cortex_m vector_catch state_err" */
case state_err:
/* UNDEFINSTR -- architectural undefined instruction */
__asm__ volatile(".hword 0xde00");
break;
- /* "cortex_m3 vector_catch chk_err" */
+ /* "cortex_m vector_catch chk_err" */
case chk_err:
/* UNALIGNED ldm */
__asm__ volatile(
@@ -112,7 +112,7 @@ int main(void)
);
break;
- /* "cortex_m3 vector_catch nocp_err" */
+ /* "cortex_m vector_catch nocp_err" */
case nocp_err:
/* NOCP ... Cortex-M3 has no coprocessors (like CP14 DCC),
* but these instructions are allowed by ARMv7-M.
@@ -120,7 +120,7 @@ int main(void)
__asm__ volatile("mrc p14, 0, r0, c0, c5, 0");
break;
- /* "cortex_m3 vector_catch mm_err" */
+ /* "cortex_m vector_catch mm_err" */
case mm_err:
/* IACCVIOL -- instruction fetch from an XN region */
__asm__ volatile(
@@ -129,7 +129,7 @@ int main(void)
);
break;
- /* "cortex_m3 vector_catch reset" */
+ /* "cortex_m vector_catch reset" */
case reset:
__asm__ volatile(
/* r1 = SYSRESETREQ */