diff options
author | Spencer Oliver <spen@spen-soft.co.uk> | 2013-02-01 15:34:51 +0000 |
---|---|---|
committer | Freddie Chopin <freddie.chopin@gmail.com> | 2013-04-28 08:55:31 +0000 |
commit | b7d2cdc0d4fc319169c60362708a67e2ff626525 (patch) | |
tree | 1ad1b79b7ff26c47023d30fee6fc7e38266f1ecc /tcl | |
parent | 564a5eb5375aa8117ee4fe48899f07490da8ae8a (diff) |
target: rename cortex_m3 to cortex_m
Rename cortex_m3 target to use a more correct cortex_m name.
This also adds a deprecated_name var so that older scripts issue a warning
to update the target name.
cfg files have also been updated to the new target name.
Change-Id: Ia8429f38e88da677249c5caa560c50f8ce56ea10
Signed-off-by: Spencer Oliver <spen@spen-soft.co.uk>
Reviewed-on: http://openocd.zylin.com/1129
Tested-by: jenkins
Reviewed-by: Freddie Chopin <freddie.chopin@gmail.com>
Diffstat (limited to 'tcl')
-rw-r--r-- | tcl/target/at91sam3XXX.cfg | 4 | ||||
-rw-r--r-- | tcl/target/at91sam3nXX.cfg | 4 | ||||
-rw-r--r-- | tcl/target/at91sam4XXX.cfg | 4 | ||||
-rw-r--r-- | tcl/target/fm3.cfg | 4 | ||||
-rw-r--r-- | tcl/target/k40.cfg | 4 | ||||
-rw-r--r-- | tcl/target/k60.cfg | 4 | ||||
-rw-r--r-- | tcl/target/lpc1788.cfg | 2 | ||||
-rw-r--r-- | tcl/target/lpc17xx.cfg | 4 | ||||
-rw-r--r-- | tcl/target/lpc1850.cfg | 4 | ||||
-rw-r--r-- | tcl/target/lpc4350.cfg | 6 | ||||
-rw-r--r-- | tcl/target/omap4430.cfg | 4 | ||||
-rw-r--r-- | tcl/target/omap4460.cfg | 4 | ||||
-rw-r--r-- | tcl/target/stellaris.cfg | 6 | ||||
-rw-r--r-- | tcl/target/stm32f1x.cfg | 4 | ||||
-rw-r--r-- | tcl/target/stm32f2x.cfg | 4 | ||||
-rw-r--r-- | tcl/target/stm32f3x.cfg | 4 | ||||
-rw-r--r-- | tcl/target/stm32f4x.cfg | 4 | ||||
-rw-r--r-- | tcl/target/stm32l.cfg | 4 |
18 files changed, 37 insertions, 37 deletions
diff --git a/tcl/target/at91sam3XXX.cfg b/tcl/target/at91sam3XXX.cfg index b90e3f01..075b462d 100644 --- a/tcl/target/at91sam3XXX.cfg +++ b/tcl/target/at91sam3XXX.cfg @@ -58,7 +58,7 @@ if { [info exists CPUTAPID] } { jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID set _TARGETNAME $_CHIPNAME.cpu -target create $_TARGETNAME cortex_m3 -endian $_ENDIAN -chain-position $_TARGETNAME +target create $_TARGETNAME cortex_m -endian $_ENDIAN -chain-position $_TARGETNAME # 16K is plenty, the smallest chip has this much $_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size 16384 -work-area-backup 0 @@ -69,4 +69,4 @@ $_TARGETNAME configure -event gdb-flash-erase-start { # if srst is not fitted use SYSRESETREQ to # perform a soft reset -cortex_m3 reset_config sysresetreq +cortex_m reset_config sysresetreq diff --git a/tcl/target/at91sam3nXX.cfg b/tcl/target/at91sam3nXX.cfg index b628103c..32f163e3 100644 --- a/tcl/target/at91sam3nXX.cfg +++ b/tcl/target/at91sam3nXX.cfg @@ -18,12 +18,12 @@ if { [info exists CPUTAPID] } { jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID set _TARGETNAME $_CHIPNAME.cpu -target create $_TARGETNAME cortex_m3 -endian little -chain-position $_TARGETNAME +target create $_TARGETNAME cortex_m -endian little -chain-position $_TARGETNAME set _FLASHNAME $_CHIPNAME.flash flash bank flash0 at91sam3 0x00400000 0 0 0 $_TARGETNAME # if srst is not fitted use SYSRESETREQ to # perform a soft reset -cortex_m3 reset_config sysresetreq +cortex_m reset_config sysresetreq diff --git a/tcl/target/at91sam4XXX.cfg b/tcl/target/at91sam4XXX.cfg index c3412184..24b3deb8 100644 --- a/tcl/target/at91sam4XXX.cfg +++ b/tcl/target/at91sam4XXX.cfg @@ -35,7 +35,7 @@ if { [info exists CPUTAPID] } { jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID set _TARGETNAME $_CHIPNAME.cpu -target create $_TARGETNAME cortex_m3 -endian $_ENDIAN -chain-position $_TARGETNAME +target create $_TARGETNAME cortex_m -endian $_ENDIAN -chain-position $_TARGETNAME # 16K is plenty, the smallest chip has this much $_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size 16384 -work-area-backup 0 @@ -46,4 +46,4 @@ $_TARGETNAME configure -event gdb-flash-erase-start { # if srst is not fitted use SYSRESETREQ to # perform a soft reset -cortex_m3 reset_config sysresetreq +cortex_m reset_config sysresetreq diff --git a/tcl/target/fm3.cfg b/tcl/target/fm3.cfg index 60967e92..e81fcc89 100644 --- a/tcl/target/fm3.cfg +++ b/tcl/target/fm3.cfg @@ -29,7 +29,7 @@ reset_config trst_only jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID set _TARGETNAME $_CHIPNAME.cpu -target create $_TARGETNAME cortex_m3 -endian $_ENDIAN -chain-position $_TARGETNAME +target create $_TARGETNAME cortex_m -endian $_ENDIAN -chain-position $_TARGETNAME # MB9BF506 has 64kB of SRAM on its main system bus $_TARGETNAME configure -work-area-phys 0x1FFF8000 -work-area-size 0x10000 -work-area-backup 0 @@ -44,4 +44,4 @@ adapter_khz 500 # if srst is not fitted use SYSRESETREQ to # perform a soft reset -cortex_m3 reset_config sysresetreq +cortex_m reset_config sysresetreq diff --git a/tcl/target/k40.cfg b/tcl/target/k40.cfg index 57aa8492..ec550288 100644 --- a/tcl/target/k40.cfg +++ b/tcl/target/k40.cfg @@ -29,11 +29,11 @@ set _TARGETNAME $_CHIPNAME.cpu swj_newdap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID -target create $_TARGETNAME cortex_m3 -chain-position $_CHIPNAME.cpu +target create $_TARGETNAME cortex_m -chain-position $_CHIPNAME.cpu $_CHIPNAME.cpu configure -event examine-start { puts "START..." ; } $_CHIPNAME.cpu configure -event examine-end { puts "END..." ; } # if srst is not fitted use SYSRESETREQ to # perform a soft reset -cortex_m3 reset_config sysresetreq +cortex_m reset_config sysresetreq diff --git a/tcl/target/k60.cfg b/tcl/target/k60.cfg index a85fa909..7ac8bb59 100644 --- a/tcl/target/k60.cfg +++ b/tcl/target/k60.cfg @@ -29,11 +29,11 @@ set _TARGETNAME $_CHIPNAME.cpu swj_newdap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID -target create $_TARGETNAME cortex_m3 -chain-position $_CHIPNAME.cpu +target create $_TARGETNAME cortex_m -chain-position $_CHIPNAME.cpu $_CHIPNAME.cpu configure -event examine-start { puts "START..." ; } $_CHIPNAME.cpu configure -event examine-end { puts "END..." ; } # if srst is not fitted use SYSRESETREQ to # perform a soft reset -cortex_m3 reset_config sysresetreq +cortex_m reset_config sysresetreq diff --git a/tcl/target/lpc1788.cfg b/tcl/target/lpc1788.cfg index 16b62c8a..e986353e 100644 --- a/tcl/target/lpc1788.cfg +++ b/tcl/target/lpc1788.cfg @@ -17,4 +17,4 @@ set CCLK 12000 source [find target/lpc17xx.cfg]; # if srst is not fitted, use SYSRESETREQ to perform a soft reset -cortex_m3 reset_config sysresetreq +cortex_m reset_config sysresetreq diff --git a/tcl/target/lpc17xx.cfg b/tcl/target/lpc17xx.cfg index a64783da..01a8cd37 100644 --- a/tcl/target/lpc17xx.cfg +++ b/tcl/target/lpc17xx.cfg @@ -57,7 +57,7 @@ jtag_ntrst_delay 200 swj_newdap $_CHIPNAME cpu -irlen 4 -expected-id $_CPUTAPID set _TARGETNAME $_CHIPNAME.cpu -target create $_TARGETNAME cortex_m3 -chain-position $_TARGETNAME +target create $_TARGETNAME cortex_m -chain-position $_TARGETNAME # The LPC17xx devices have 8/16/32kB of SRAM In the ARMv7-M "Code" area (at 0x10000000) $_TARGETNAME configure -work-area-phys 0x10000000 -work-area-size $_CPURAMSIZE @@ -94,4 +94,4 @@ $_TARGETNAME configure -event reset-init { # if srst is not fitted use VECTRESET to # perform a soft reset - SYSRESETREQ is not supported -cortex_m3 reset_config vectreset +cortex_m reset_config vectreset diff --git a/tcl/target/lpc1850.cfg b/tcl/target/lpc1850.cfg index 1ea7a49e..94aec38f 100644 --- a/tcl/target/lpc1850.cfg +++ b/tcl/target/lpc1850.cfg @@ -24,8 +24,8 @@ if { [info exists M3_JTAG_TAPID] } { jtag newtap $_CHIPNAME m3 -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_M3_JTAG_TAPID set _TARGETNAME $_CHIPNAME.m3 -target create $_TARGETNAME cortex_m3 -endian $_ENDIAN -chain-position $_TARGETNAME +target create $_TARGETNAME cortex_m -endian $_ENDIAN -chain-position $_TARGETNAME # if srst is not fitted use SYSRESETREQ to # perform a soft reset -cortex_m3 reset_config sysresetreq +cortex_m reset_config sysresetreq diff --git a/tcl/target/lpc4350.cfg b/tcl/target/lpc4350.cfg index fbbea97d..47f25296 100644 --- a/tcl/target/lpc4350.cfg +++ b/tcl/target/lpc4350.cfg @@ -40,12 +40,12 @@ jtag newtap $_CHIPNAME m4 -irlen 4 -ircapture 0x1 -irmask 0xf \ jtag newtap $_CHIPNAME m0 -irlen 4 -ircapture 0x1 -irmask 0xf \ -expected-id $_M0_JTAG_TAPID -target create $_CHIPNAME.m4 cortex_m3 -chain-position $_CHIPNAME.m4 -target create $_CHIPNAME.m0 cortex_m3 -chain-position $_CHIPNAME.m0 +target create $_CHIPNAME.m4 cortex_m -chain-position $_CHIPNAME.m4 +target create $_CHIPNAME.m0 cortex_m -chain-position $_CHIPNAME.m0 # on this CPU we should use VECTRESET to perform a soft reset and # manually reset the periphery # SRST or SYSRESETREQ disable the debug interface for the time of # the reset and will not fit our requirements for a consistent debug # session -cortex_m3 reset_config vectreset +cortex_m reset_config vectreset diff --git a/tcl/target/omap4430.cfg b/tcl/target/omap4430.cfg index f16d7488..2e9f5543 100644 --- a/tcl/target/omap4430.cfg +++ b/tcl/target/omap4430.cfg @@ -104,8 +104,8 @@ $_TARGETNAME configure -work-area-phys 0x40300000 -work-area-size 0x1000 # # M3 targets, separate TAP/DAP for each core # -target create $_CHIPNAME.m30 cortex_m3 -chain-position $_CHIPNAME.m30_dap -target create $_CHIPNAME.m31 cortex_m3 -chain-position $_CHIPNAME.m31_dap +target create $_CHIPNAME.m30 cortex_m -chain-position $_CHIPNAME.m30_dap +target create $_CHIPNAME.m31 cortex_m -chain-position $_CHIPNAME.m31_dap # Once the JRC is up, enable our TAPs diff --git a/tcl/target/omap4460.cfg b/tcl/target/omap4460.cfg index 6e8acda5..5fdd654d 100644 --- a/tcl/target/omap4460.cfg +++ b/tcl/target/omap4460.cfg @@ -104,8 +104,8 @@ $_TARGETNAME configure -work-area-phys 0x40300000 -work-area-size 0x1000 # # M3 targets, separate TAP/DAP for each core # -target create $_CHIPNAME.m30 cortex_m3 -chain-position $_CHIPNAME.m30_dap -target create $_CHIPNAME.m31 cortex_m3 -chain-position $_CHIPNAME.m31_dap +target create $_CHIPNAME.m30 cortex_m -chain-position $_CHIPNAME.m30_dap +target create $_CHIPNAME.m31 cortex_m -chain-position $_CHIPNAME.m31_dap # Once the JRC is up, enable our TAPs diff --git a/tcl/target/stellaris.cfg b/tcl/target/stellaris.cfg index 06f27c56..9804bde7 100644 --- a/tcl/target/stellaris.cfg +++ b/tcl/target/stellaris.cfg @@ -52,7 +52,7 @@ if { [info exists WORKAREASIZE] } { } set _TARGETNAME $_CHIPNAME.cpu -target create $_TARGETNAME cortex_m3 -chain-position $_CHIPNAME.cpu +target create $_TARGETNAME cortex_m -chain-position $_CHIPNAME.cpu # 8K working area at base of ram, not backed up # @@ -157,11 +157,11 @@ $_TARGETNAME configure -event reset-start { if {$device_class == 0 || $device_class == 1 || $device_class == 3 || $device_class == 5} { # Sandstorm, Fury, DustDevil and Blizzard are able to use NVIC SYSRESETREQ - cortex_m3 reset_config sysresetreq + cortex_m reset_config sysresetreq } else { # Tempest and Firestorm default to using NVIC VECTRESET # peripherals will need reseting manually, see proc reset_peripherals - cortex_m3 reset_config vectreset + cortex_m reset_config vectreset # reset peripherals, based on code in # http://www.ti.com/lit/er/spmz573a/spmz573a.pdf diff --git a/tcl/target/stm32f1x.cfg b/tcl/target/stm32f1x.cfg index a686e51a..7d3f42f3 100644 --- a/tcl/target/stm32f1x.cfg +++ b/tcl/target/stm32f1x.cfg @@ -68,7 +68,7 @@ jtag newtap $_CHIPNAME bs -irlen 5 -expected-id $_BSTAPID1 \ -expected-id $_BSTAPID8 -expected-id $_BSTAPID9 set _TARGETNAME $_CHIPNAME.cpu -target create $_TARGETNAME cortex_m3 -endian $_ENDIAN -chain-position $_TARGETNAME +target create $_TARGETNAME cortex_m -endian $_ENDIAN -chain-position $_TARGETNAME $_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE -work-area-backup 0 @@ -78,4 +78,4 @@ flash bank $_FLASHNAME stm32f1x 0x08000000 0 0 0 $_TARGETNAME # if srst is not fitted use SYSRESETREQ to # perform a soft reset -cortex_m3 reset_config sysresetreq +cortex_m reset_config sysresetreq diff --git a/tcl/target/stm32f2x.cfg b/tcl/target/stm32f2x.cfg index cfd6274e..43a944c1 100644 --- a/tcl/target/stm32f2x.cfg +++ b/tcl/target/stm32f2x.cfg @@ -52,7 +52,7 @@ if { [info exists BSTAPID] } { jtag newtap $_CHIPNAME bs -irlen 5 -expected-id $_BSTAPID set _TARGETNAME $_CHIPNAME.cpu -target create $_TARGETNAME cortex_m3 -endian $_ENDIAN -chain-position $_TARGETNAME +target create $_TARGETNAME cortex_m -endian $_ENDIAN -chain-position $_TARGETNAME $_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE -work-area-backup 0 @@ -61,4 +61,4 @@ flash bank $_FLASHNAME stm32f2x 0 0 0 0 $_TARGETNAME # if srst is not fitted use SYSRESETREQ to # perform a soft reset -cortex_m3 reset_config sysresetreq +cortex_m reset_config sysresetreq diff --git a/tcl/target/stm32f3x.cfg b/tcl/target/stm32f3x.cfg index 31993ff8..d092b6c8 100644 --- a/tcl/target/stm32f3x.cfg +++ b/tcl/target/stm32f3x.cfg @@ -52,7 +52,7 @@ if { [info exists BSTAPID] } { jtag newtap $_CHIPNAME bs -irlen 5 -expected-id $_BSTAPID1 -expected-id $_BSTAPID2 set _TARGETNAME $_CHIPNAME.cpu -target create $_TARGETNAME cortex_m3 -endian $_ENDIAN -chain-position $_TARGETNAME +target create $_TARGETNAME cortex_m -endian $_ENDIAN -chain-position $_TARGETNAME $_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE -work-area-backup 0 @@ -61,4 +61,4 @@ flash bank $_FLASHNAME stm32f1x 0 0 0 0 $_TARGETNAME # if srst is not fitted use SYSRESETREQ to # perform a soft reset -cortex_m3 reset_config sysresetreq +cortex_m reset_config sysresetreq diff --git a/tcl/target/stm32f4x.cfg b/tcl/target/stm32f4x.cfg index 16beaa46..374c3371 100644 --- a/tcl/target/stm32f4x.cfg +++ b/tcl/target/stm32f4x.cfg @@ -51,7 +51,7 @@ if { [info exists BSTAPID] } { jtag newtap $_CHIPNAME bs -irlen 5 -expected-id $_BSTAPID set _TARGETNAME $_CHIPNAME.cpu -target create $_TARGETNAME cortex_m3 -endian $_ENDIAN -chain-position $_TARGETNAME +target create $_TARGETNAME cortex_m -endian $_ENDIAN -chain-position $_TARGETNAME $_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE -work-area-backup 0 @@ -60,4 +60,4 @@ flash bank $_FLASHNAME stm32f2x 0 0 0 0 $_TARGETNAME # if srst is not fitted use SYSRESETREQ to # perform a soft reset -cortex_m3 reset_config sysresetreq +cortex_m reset_config sysresetreq diff --git a/tcl/target/stm32l.cfg b/tcl/target/stm32l.cfg index eea082e6..8e6a10e1 100644 --- a/tcl/target/stm32l.cfg +++ b/tcl/target/stm32l.cfg @@ -48,7 +48,7 @@ if { [info exists BSTAPID] } { jtag newtap $_CHIPNAME bs -irlen 5 -expected-id $_BSTAPID set _TARGETNAME $_CHIPNAME.cpu -target create $_TARGETNAME cortex_m3 -endian $_ENDIAN -chain-position $_TARGETNAME +target create $_TARGETNAME cortex_m -endian $_ENDIAN -chain-position $_TARGETNAME $_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE -work-area-backup 0 @@ -59,7 +59,7 @@ flash bank $_FLASHNAME stm32lx 0x08000000 0 0 0 $_TARGETNAME # if srst is not fitted use SYSRESETREQ to # perform a soft reset -cortex_m3 reset_config sysresetreq +cortex_m reset_config sysresetreq proc stm32l_enable_HSI {} { # Enable HSI as clock source |