diff options
| author | Paul Fertser <fercerpav@gmail.com> | 2013-12-30 22:26:36 +0400 |
|---|---|---|
| committer | Spencer Oliver <spen@spen-soft.co.uk> | 2014-01-08 22:18:18 +0000 |
| commit | faedb1477292dda20267adbdcf6536da3ec77502 (patch) | |
| tree | 0f58093c7504b58091a6860a344564bf3a64cffb /tcl/target | |
| parent | 436f66b46327296ce818c3265f09381b2b0af7a7 (diff) | |
tcl: add bcm47xx config and Asus RT-N16 board using it
This adds the bcm47xx config with the special undocumented trick to
put it into standard EJTAG mode from the mystic "LV mode".
The RAM setup is not done as it would require considerable efforts
without much practical gain.
The only issue I noticed so far is that "reset" doesn't actually reset
the chip.
Unfortunately, it's unclear how to make it work properly with SRST as
OpenOCD asserts it in MIPS-specific code so the device will enter LV
mode again but the LV tap is already disabled by that time, so it's
not possible to send the magic command again.
Anyway, this config is more than enough to "recover" any RT-N16
provided the hardware is not damaged.
Change-Id: I0894e339763e6d20d1c93341c597382b479d039b
Signed-off-by: Paul Fertser <fercerpav@gmail.com>
Reviewed-on: http://openocd.zylin.com/1849
Tested-by: jenkins
Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
Diffstat (limited to 'tcl/target')
| -rw-r--r-- | tcl/target/bcm4718.cfg | 5 | ||||
| -rw-r--r-- | tcl/target/bcm47xx.cfg | 21 |
2 files changed, 26 insertions, 0 deletions
diff --git a/tcl/target/bcm4718.cfg b/tcl/target/bcm4718.cfg new file mode 100644 index 00000000..8193914a --- /dev/null +++ b/tcl/target/bcm4718.cfg @@ -0,0 +1,5 @@ +set _CHIPNAME bcm4718 +set _LVTAPID 0x1471617f +set _CPUID 0x0008c17f + +source [find target/bcm47xx.cfg] diff --git a/tcl/target/bcm47xx.cfg b/tcl/target/bcm47xx.cfg new file mode 100644 index 00000000..0132bb80 --- /dev/null +++ b/tcl/target/bcm47xx.cfg @@ -0,0 +1,21 @@ +echo "Forcing reset_config to none to prevent OpenOCD from pulling SRST after the switch from LV is already performed" +reset_config none + +jtag newtap $_CHIPNAME-lv tap -irlen 32 -ircapture 0x1 -irmask 0x1f -expected-id $_LVTAPID -expected-id $_CPUID +jtag configure $_CHIPNAME-lv.tap -event setup "jtag tapenable $_CHIPNAME.cpu" +jtag configure $_CHIPNAME-lv.tap -event tap-disable {} + +jtag newtap $_CHIPNAME cpu -irlen 5 -ircapture 0x1 -irmask 0x1f -expected-id $_CPUID -disable +jtag configure $_CHIPNAME.cpu -event tap-enable "switch_lv_to_ejtag" + +set _TARGETNAME $_CHIPNAME.cpu +target create $_TARGETNAME mips_m4k -endian little -chain-position $_TARGETNAME + +proc switch_lv_to_ejtag {} { + global _CHIPNAME + poll 0 + irscan $_CHIPNAME-lv.tap 0x143ff3a + drscan $_CHIPNAME-lv.tap 32 1 + jtag tapdisable $_CHIPNAME-lv.tap + poll 1 +} |