diff options
author | Spencer Oliver <spen@spen-soft.co.uk> | 2013-08-06 13:12:10 +0100 |
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committer | Spencer Oliver <spen@spen-soft.co.uk> | 2014-01-09 15:22:42 +0000 |
commit | acc4bb83fd1f26a677fdc2c8ccdc7a235f877d2d (patch) | |
tree | 4a8ac63e67ef83e7514dc25e05b73b39c5f81cc0 /tcl/target/stm32f0x.cfg | |
parent | 4dc8cd201c667bac72bc083ef1fa1b285eb093fc (diff) |
cfg: add stm32 cmsis-dap compliant config
Change-Id: I3cfb21fdcef830e22b03bf4b5d58993728cc7475
Signed-off-by: Spencer Oliver <spen@spen-soft.co.uk>
Reviewed-on: http://openocd.zylin.com/1543
Tested-by: jenkins
Diffstat (limited to 'tcl/target/stm32f0x.cfg')
-rw-r--r-- | tcl/target/stm32f0x.cfg | 55 |
1 files changed, 55 insertions, 0 deletions
diff --git a/tcl/target/stm32f0x.cfg b/tcl/target/stm32f0x.cfg new file mode 100644 index 00000000..104dcb9c --- /dev/null +++ b/tcl/target/stm32f0x.cfg @@ -0,0 +1,55 @@ +# script for stm32f0x family + +# +# stm32 devices support SWD transports only. +# +source [find target/swj-dp.tcl] + +if { [info exists CHIPNAME] } { + set _CHIPNAME $CHIPNAME +} else { + set _CHIPNAME stm32f0x +} + +if { [info exists ENDIAN] } { + set _ENDIAN $ENDIAN +} else { + set _ENDIAN little +} + +# Work-area is a space in RAM used for flash programming +# By default use 4kB +if { [info exists WORKAREASIZE] } { + set _WORKAREASIZE $WORKAREASIZE +} else { + set _WORKAREASIZE 0x1000 +} + +#jtag scan chain +if { [info exists CPUTAPID] } { + set _CPUTAPID $CPUTAPID +} else { + # See STM Document RM0091 + # Section 29.5.3 + set _CPUTAPID 0x0bb11477 +} + +swj_newdap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID + +set _TARGETNAME $_CHIPNAME.cpu +target create $_TARGETNAME cortex_m -endian $_ENDIAN -chain-position $_TARGETNAME + +$_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE -work-area-backup 0 + +# flash size will be probed +set _FLASHNAME $_CHIPNAME.flash +flash bank $_FLASHNAME stm32f1x 0x08000000 0 0 0 $_TARGETNAME + +# adapter speed should be <= F_CPU/6. F_CPU after reset is 8MHz, so use F_JTAG = 1MHz +adapter_khz 1000 + +adapter_nsrst_delay 100 + +# if srst is not fitted use SYSRESETREQ to +# perform a soft reset +cortex_m reset_config sysresetreq |