diff options
| author | Matthias Welwarsky <matthias.welwarsky@sysgo.com> | 2018-03-23 21:17:29 +0100 |
|---|---|---|
| committer | Matthias Welwarsky <matthias@welwarsky.de> | 2018-03-30 09:58:21 +0100 |
| commit | 2231da8ec4e7d7ae9b652f3dd1a7104f5a110f3f (patch) | |
| tree | 72623961be532d0f35e292a2fe9e8f1cf4e09c1a /tcl/target/omap4460.cfg | |
| parent | 72740904568414bb4a9192fe89034bae3b1a9e45 (diff) | |
target: restructure dap support
- add 'dap create' command to create dap instances
- move all dap subcmmand into the dap instance commands
- keep 'dap info' for convenience
- change all armv7 and armv8 targets to take a dap
instance instead of a jtag chain position
- restructure tap/dap/target relations, jtag tap no
longer references the dap, daps are now independently
created and initialized.
- clean up swd connect
- re-initialize DAP also on JTAG errors (e.g. after reset,
power cycle)
- update documentation
- update target files
Change-Id: I322cf3969b5407c25d1d3962f9d9b9bc1df067d9
Signed-off-by: Matthias Welwarsky <matthias.welwarsky@sysgo.com>
Reviewed-on: http://openocd.zylin.com/4468
Tested-by: jenkins
Reviewed-by: Matthias Welwarsky <matthias@welwarsky.de>
Diffstat (limited to 'tcl/target/omap4460.cfg')
| -rw-r--r-- | tcl/target/omap4460.cfg | 27 |
1 files changed, 15 insertions, 12 deletions
diff --git a/tcl/target/omap4460.cfg b/tcl/target/omap4460.cfg index 9c40e62d..218eb64e 100644 --- a/tcl/target/omap4460.cfg +++ b/tcl/target/omap4460.cfg @@ -22,9 +22,9 @@ if { [info exists DAP_TAPID] } { set _DAP_TAPID 0x3BA00477 } -jtag newtap $_CHIPNAME dap -irlen 4 -ircapture 0x1 -irmask 0xf \ +jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf \ -expected-id $_DAP_TAPID -disable -jtag configure $_CHIPNAME.dap -event tap-enable \ +jtag configure $_CHIPNAME.cpu -event tap-enable \ "icepick_c_tapenable $_CHIPNAME.jrc 9" @@ -37,14 +37,14 @@ if { [info exists M3_DAP_TAPID] } { set _M3_DAP_TAPID 0x4BA00477 } -jtag newtap $_CHIPNAME m31_dap -irlen 4 -ircapture 0x1 -irmask 0xf \ +jtag newtap $_CHIPNAME m31 -irlen 4 -ircapture 0x1 -irmask 0xf \ -expected-id $_M3_DAP_TAPID -disable -jtag configure $_CHIPNAME.m31_dap -event tap-enable \ +jtag configure $_CHIPNAME.m31 -event tap-enable \ "icepick_c_tapenable $_CHIPNAME.jrc 5" -jtag newtap $_CHIPNAME m30_dap -irlen 4 -ircapture 0x1 -irmask 0xf \ +jtag newtap $_CHIPNAME m30 -irlen 4 -ircapture 0x1 -irmask 0xf \ -expected-id $_M3_DAP_TAPID -disable -jtag configure $_CHIPNAME.m30_dap -event tap-enable \ +jtag configure $_CHIPNAME.m30 -event tap-enable \ "icepick_c_tapenable $_CHIPNAME.jrc 4" @@ -94,7 +94,8 @@ set _coreid 0 set _dbgbase [expr 0x80000000 | ($_coreid << 13)] echo "Using dbgbase = [format 0x%x $_dbgbase]" -target create $_TARGETNAME cortex_a -chain-position $_CHIPNAME.dap \ +dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu +target create $_TARGETNAME cortex_a -dap $_CHIPNAME.dap \ -coreid 0 -dbgbase $_dbgbase # SRAM: 56KiB at 0x4030.0000 @@ -104,15 +105,17 @@ $_TARGETNAME configure -work-area-phys 0x40300000 -work-area-size 0x1000 # # M3 targets, separate TAP/DAP for each core # -target create $_CHIPNAME.m30 cortex_m -chain-position $_CHIPNAME.m30_dap -target create $_CHIPNAME.m31 cortex_m -chain-position $_CHIPNAME.m31_dap +dap create $_CHIPNAME.m30_dap -chain-position $_CHIPNAME.m30 +dap create $_CHIPNAME.m31_dap -chain-position $_CHIPNAME.m31 +target create $_CHIPNAME.m30 cortex_m -dap $_CHIPNAME.m30_dap +target create $_CHIPNAME.m31 cortex_m -dap $_CHIPNAME.m31_dap # Once the JRC is up, enable our TAPs jtag configure $_CHIPNAME.jrc -event setup " - jtag tapenable $_CHIPNAME.dap - jtag tapenable $_CHIPNAME.m30_dap - jtag tapenable $_CHIPNAME.m31_dap + jtag tapenable $_CHIPNAME.cpu + jtag tapenable $_CHIPNAME.m30 + jtag tapenable $_CHIPNAME.m31 " # Assume SRST is unavailable (e.g. TI-14 JTAG), so we must assert reset |