diff options
| author | Paul Fertser <fercerpav@gmail.com> | 2015-03-15 10:18:55 +0300 |
|---|---|---|
| committer | Paul Fertser <fercerpav@gmail.com> | 2015-04-16 20:24:50 +0100 |
| commit | 5387d616a3d1b4550f9acecda26ead380d37dedf (patch) | |
| tree | 6f9e73926f732cc7908fc44a08fab9c769550abb /src/target | |
| parent | da7b65a93becd0d45d2806e14f0c0b1e3dd6dfd5 (diff) | |
Fix several format specifiers errors exposed by arm-none-eabi
Change-Id: I1fe5c5c0b22cc23deedcf13ad5183c957551a1b7
Signed-off-by: Paul Fertser <fercerpav@gmail.com>
Reviewed-on: http://openocd.zylin.com/2719
Tested-by: jenkins
Diffstat (limited to 'src/target')
| -rw-r--r-- | src/target/arm_adi_v5.c | 2 | ||||
| -rw-r--r-- | src/target/cortex_a.c | 4 | ||||
| -rw-r--r-- | src/target/mips_ejtag.c | 6 |
3 files changed, 6 insertions, 6 deletions
diff --git a/src/target/arm_adi_v5.c b/src/target/arm_adi_v5.c index 3df39f9e..f7e58d08 100644 --- a/src/target/arm_adi_v5.c +++ b/src/target/arm_adi_v5.c @@ -992,7 +992,7 @@ static int dap_rom_display(struct command_context *cmd_ctx, uint32_t c_cid0, c_cid1, c_cid2, c_cid3; uint32_t c_pid0, c_pid1, c_pid2, c_pid3, c_pid4; uint32_t component_base; - unsigned part_num; + uint32_t part_num; const char *type, *full; component_base = (dbgbase & 0xFFFFF000) + (romentry & 0xFFFFF000); diff --git a/src/target/cortex_a.c b/src/target/cortex_a.c index 7ecf428d..ed9b2b29 100644 --- a/src/target/cortex_a.c +++ b/src/target/cortex_a.c @@ -238,7 +238,7 @@ static int cortex_a_init_debug_access(struct target *target) the registers in the Core Power Domain */ retval = mem_ap_sel_read_atomic_u32(swjdp, armv7a->debug_ap, armv7a->debug_base + CPUDBG_PRSR, &dbg_osreg); - LOG_DEBUG("target->coreid %d DBGPRSR 0x%x ", target->coreid, dbg_osreg); + LOG_DEBUG("target->coreid %" PRId32 " DBGPRSR 0x%" PRIx32, target->coreid, dbg_osreg); if (retval != ERROR_OK) return retval; @@ -2954,7 +2954,7 @@ static int cortex_a_examine_first(struct target *target) if (retval != ERROR_OK) return retval; - LOG_DEBUG("target->coreid %d DBGPRSR 0x%" PRIx32, target->coreid, dbg_osreg); + LOG_DEBUG("target->coreid %" PRId32 " DBGPRSR 0x%" PRIx32, target->coreid, dbg_osreg); armv7a->arm.core_type = ARM_MODE_MON; retval = cortex_a_dpm_setup(cortex_a, didr); diff --git a/src/target/mips_ejtag.c b/src/target/mips_ejtag.c index f6cd4510..2a16193f 100644 --- a/src/target/mips_ejtag.c +++ b/src/target/mips_ejtag.c @@ -352,9 +352,9 @@ static void ejtag_v20_print_imp(struct mips_ejtag *ejtag_info) EJTAG_IMP_HAS(EJTAG_V20_IMP_NOPB) ? " noPB" : " PB", EJTAG_IMP_HAS(EJTAG_V20_IMP_NODB) ? " noDB" : " DB", EJTAG_IMP_HAS(EJTAG_V20_IMP_NOIB) ? " noIB" : " IB"); - LOG_DEBUG("EJTAG v2.0: Break Channels: %i", - (ejtag_info->impcode >> EJTAG_V20_IMP_BCHANNELS_SHIFT) & - EJTAG_V20_IMP_BCHANNELS_MASK); + LOG_DEBUG("EJTAG v2.0: Break Channels: %" PRIu8, + (uint8_t)((ejtag_info->impcode >> EJTAG_V20_IMP_BCHANNELS_SHIFT) & + EJTAG_V20_IMP_BCHANNELS_MASK)); } static void ejtag_v26_print_imp(struct mips_ejtag *ejtag_info) |