diff options
author | Antonio Borneo <borneo.antonio@gmail.com> | 2019-04-15 22:32:32 +0200 |
---|---|---|
committer | Matthias Welwarsky <matthias@welwarsky.de> | 2019-04-24 14:09:32 +0100 |
commit | d870ecf5ff4a71e119418fabe8a250a2bab61357 (patch) | |
tree | 7b6e6d60194812012f7ac31040992cbf0c162ccc /src/target/cortex_a.c | |
parent | d3a9e535d52bebf9973babe564c09797c71a2fc2 (diff) |
target/cortex_a: check dscr before timeout
In function cortex_a_wait_dscr_bits() the last read on dscr gets
ignored in case of timeout, even if it finally provides the value
that would trigger a successful return.
Check the returned value before testing the timeout.
Also, print a message on failure reading dscr.
Change-Id: I261ac1545113db39374833a55be911a4da71d893
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: http://openocd.zylin.com/5112
Tested-by: jenkins
Reviewed-by: Matthias Welwarsky <matthias@welwarsky.de>
Diffstat (limited to 'src/target/cortex_a.c')
-rw-r--r-- | src/target/cortex_a.c | 14 |
1 files changed, 11 insertions, 3 deletions
diff --git a/src/target/cortex_a.c b/src/target/cortex_a.c index 8ed81b78..587cbba0 100644 --- a/src/target/cortex_a.c +++ b/src/target/cortex_a.c @@ -1765,14 +1765,22 @@ static int cortex_a_wait_dscr_bits(struct target *target, uint32_t mask, { /* Waits until the specified bit(s) of DSCR take on a specified value. */ struct armv7a_common *armv7a = target_to_armv7a(target); - int64_t then = timeval_ms(); + int64_t then; int retval; - while ((*dscr & mask) != value) { + if ((*dscr & mask) == value) + return ERROR_OK; + + then = timeval_ms(); + while (1) { retval = mem_ap_read_atomic_u32(armv7a->debug_ap, armv7a->debug_base + CPUDBG_DSCR, dscr); - if (retval != ERROR_OK) + if (retval != ERROR_OK) { + LOG_ERROR("Could not read DSCR register"); return retval; + } + if ((*dscr & mask) == value) + break; if (timeval_ms() > then + 1000) { LOG_ERROR("timeout waiting for DSCR bit change"); return ERROR_FAIL; |