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| author | Matthias Welwarsky <matthias.welwarsky@sysgo.com> | 2016-10-20 13:20:26 +0200 |
|---|---|---|
| committer | Matthias Welwarsky <matthias.welwarsky@sysgo.com> | 2017-02-10 14:18:34 +0100 |
| commit | 62c2eb4b284e0a3deb2aad7163354200bd93e634 (patch) | |
| tree | 8dce6921caaeb3843015c845f6e03ec05ef14b0f /src/target/armv8_opcodes.c | |
| parent | 946958cb723f0b123505234275ce9a653ddbfbd2 (diff) | |
aarch64: cache identification for aarch32 state
Use proper T32 opcodes for cache identification when the PE is in
Aarch32 state
Change-Id: I9cd9169409889273a3fd61167f388e68d8dde86d
Signed-off-by: Matthias Welwarsky <matthias.welwarsky@sysgo.com>
Diffstat (limited to 'src/target/armv8_opcodes.c')
| -rw-r--r-- | src/target/armv8_opcodes.c | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/src/target/armv8_opcodes.c b/src/target/armv8_opcodes.c index 75ea9461..2b42cdf3 100644 --- a/src/target/armv8_opcodes.c +++ b/src/target/armv8_opcodes.c @@ -24,6 +24,7 @@ #include "armv8_opcodes.h" static const uint32_t a64_opcodes[ARMV8_OPC_NUM] = { + [READ_REG_CTR] = ARMV8_MRS(SYSTEM_CTR, 0), [READ_REG_CLIDR] = ARMV8_MRS(SYSTEM_CLIDR, 0), [READ_REG_CSSELR] = ARMV8_MRS(SYSTEM_CSSELR, 0), [READ_REG_CCSIDR] = ARMV8_MRS(SYSTEM_CCSIDR, 0), @@ -39,6 +40,7 @@ static const uint32_t a64_opcodes[ARMV8_OPC_NUM] = { }; static const uint32_t t32_opcodes[ARMV8_OPC_NUM] = { + [READ_REG_CTR] = ARMV4_5_MRC(15, 0, 0, 0, 0, 1), [READ_REG_CLIDR] = ARMV4_5_MRC(15, 1, 0, 0, 0, 1), [READ_REG_CSSELR] = ARMV4_5_MRC(15, 2, 0, 0, 0, 0), [READ_REG_CCSIDR] = ARMV4_5_MRC(15, 1, 0, 0, 0, 0), |