diff options
| author | Evan Hunter <ehunter@broadcom.com> | 2012-10-23 15:48:41 +1100 |
|---|---|---|
| committer | Spencer Oliver <spen@spen-soft.co.uk> | 2013-03-15 15:50:42 +0000 |
| commit | 927e53f8d5e6ebaf52be82cb7300cbbb471a92bb (patch) | |
| tree | 11bbaffaeb2088d450135eb52515b94da17f795a /src/target/arm_opcodes.h | |
| parent | 700e7605fe63571f6b912ce994c2f1eb1fd4fe92 (diff) | |
cortex_a : optimize apb read/write access.
Rewrite: Adheres more closely to 'fast read/write' examples in TRM.
up to 50x faster
Change-Id: Ieb4da57d8367628f3e7306827a5b1f0ab550e641
Signed-off-by: Evan Hunter <ehunter@broadcom.com>
Reviewed-on: http://openocd.zylin.com/903
Tested-by: jenkins
Reviewed-by: Michel JAOUEN <michel.jaouen@stericsson.com>
Reviewed-by: Freddie Chopin <freddie.chopin@gmail.com>
Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
Diffstat (limited to 'src/target/arm_opcodes.h')
| -rw-r--r-- | src/target/arm_opcodes.h | 30 |
1 files changed, 30 insertions, 0 deletions
diff --git a/src/target/arm_opcodes.h b/src/target/arm_opcodes.h index 12a9ca8d..976cab94 100644 --- a/src/target/arm_opcodes.h +++ b/src/target/arm_opcodes.h @@ -133,6 +133,36 @@ */ #define ARMV4_5_BX(Rm) (0xe12fff10 | (Rm)) +/* Store data from coprocessor to consecutive memory + * See Armv7-A arch doc section A8.6.187 + * P: 1=index mode (offset from Rn) + * U: 1=add, 0=subtract Rn address with imm + * D: Opcode D encoding + * W: write back the offset start address to the Rn register + * CP: Coprocessor number (4 bits) + * CRd: Coprocessor source register (4 bits) + * Rn: Base register for memory address (4 bits) + * imm: Immediate value (0 - 1020, must be divisible by 4) + */ +#define ARMV4_5_STC(P, U, D, W, CP, CRd, Rn, imm) \ + (0xec000000 | ((P) << 24) | ((U) << 23) | ((D) << 22) | \ + ((W) << 21) | ((Rn) << 16) | ((CRd) << 12) | ((CP) << 8) | ((imm)>>2)) + +/* Loads data from consecutive memory to coprocessor + * See Armv7-A arch doc section A8.6.51 + * P: 1=index mode (offset from Rn) + * U: 1=add, 0=subtract Rn address with imm + * D: Opcode D encoding + * W: write back the offset start address to the Rn register + * CP: Coprocessor number (4 bits) + * CRd: Coprocessor dest register (4 bits) + * Rn: Base register for memory address (4 bits) + * imm: Immediate value (0 - 1020, must be divisible by 4) + */ +#define ARMV4_5_LDC(P, U, D, W, CP, CRd, Rn, imm) \ + (0xec100000 | ((P) << 24) | ((U) << 23) | ((D) << 22) | \ + ((W) << 21) | ((Rn) << 16) | ((CRd) << 12) | ((CP) << 8) | ((imm) >> 2)) + /* Move to ARM register from coprocessor * CP: Coprocessor number * op1: Coprocessor opcode |