diff options
| author | Paul Fertser <fercerpav@gmail.com> | 2018-05-22 12:04:31 +0300 |
|---|---|---|
| committer | Matthias Welwarsky <matthias@welwarsky.de> | 2018-05-30 09:36:46 +0100 |
| commit | b50fa9a19d0b600d26b6cbca57cd94c7b89f941c (patch) | |
| tree | b877109bddff78d9e6594edf70de5f457d5203cc /src/target/arm_disassembler.c | |
| parent | dae1ec1278fcac5369843b52db5eb12c2180d624 (diff) | |
Fix warnings exposed by GCC8
gcc (GCC) 8.1.0 generates new warnings and thus fails the build.
The ARM disassembler warnings actually exposed a bug in SMALW, SMULW and
SMUL instructions decoding.
Reported by Eimers on IRC.
Change-Id: I200c70f75a9e07a1f13a592addc1c5fb37714440
Signed-off-by: Paul Fertser <fercerpav@gmail.com>
Reviewed-on: http://openocd.zylin.com/4526
Tested-by: jenkins
Reviewed-by: Jiri Kastner <cz172638@gmail.com>
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-by: Matthias Welwarsky <matthias@welwarsky.de>
Diffstat (limited to 'src/target/arm_disassembler.c')
| -rw-r--r-- | src/target/arm_disassembler.c | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/src/target/arm_disassembler.c b/src/target/arm_disassembler.c index 8e783d34..17948d6d 100644 --- a/src/target/arm_disassembler.c +++ b/src/target/arm_disassembler.c @@ -1549,7 +1549,7 @@ static int evaluate_misc_instr(uint32_t opcode, } /* SMLAW < y> */ - if (((opcode & 0x00600000) == 0x00100000) && (x == 0)) { + if (((opcode & 0x00600000) == 0x00200000) && (x == 0)) { uint8_t Rd, Rm, Rs, Rn; instruction->type = ARM_SMLAWy; Rd = (opcode & 0xf0000) >> 16; @@ -1571,7 +1571,7 @@ static int evaluate_misc_instr(uint32_t opcode, } /* SMUL < x><y> */ - if ((opcode & 0x00600000) == 0x00300000) { + if ((opcode & 0x00600000) == 0x00600000) { uint8_t Rd, Rm, Rs; instruction->type = ARM_SMULxy; Rd = (opcode & 0xf0000) >> 16; @@ -1592,7 +1592,7 @@ static int evaluate_misc_instr(uint32_t opcode, } /* SMULW < y> */ - if (((opcode & 0x00600000) == 0x00100000) && (x == 1)) { + if (((opcode & 0x00600000) == 0x00200000) && (x == 1)) { uint8_t Rd, Rm, Rs; instruction->type = ARM_SMULWy; Rd = (opcode & 0xf0000) >> 16; |