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authorSteven Stallion <stallion@squareup.com>2018-10-24 21:29:03 -0500
committerMatthias Welwarsky <matthias@welwarsky.de>2018-12-12 08:47:44 +0000
commitc5eb99082535574167294443be1e60077e3f6246 (patch)
tree4c2421624ae987ffe38321e9360bb41582953f6c /src/target/Makefile.am
parent7ae6b04b982428e6ae3d6daa6f5e77482a460c40 (diff)
esirisc: support eSi-Trace
This patch adds support for instruction tracing to eSi-RISC targets. The command interface is borrowed heavily from ETM; eSi-Trace uses a less sophisticated model for tracing, however the setup and usage is similar. This patch also cleans up the command interfaces of the other esirisc command groups and adds additional debugging information to log messages when dealing with CSRs. This patch "finalizes" support for 32-bit eSi-RISC targets. Change-Id: Ia2a9de79a3c7c066240b5212721fb1b7584a9a45 Signed-off-by: Steven Stallion <stallion@squareup.com> Reviewed-on: http://openocd.zylin.com/4780 Tested-by: jenkins Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
Diffstat (limited to 'src/target/Makefile.am')
-rw-r--r--src/target/Makefile.am6
1 files changed, 4 insertions, 2 deletions
diff --git a/src/target/Makefile.am b/src/target/Makefile.am
index 8e9fcb27..afa5f49b 100644
--- a/src/target/Makefile.am
+++ b/src/target/Makefile.am
@@ -143,7 +143,8 @@ INTEL_IA32_SRC = \
ESIRISC_SRC = \
%D%/esirisc.c \
- %D%/esirisc_jtag.c
+ %D%/esirisc_jtag.c \
+ %D%/esirisc_trace.c
%C%_libtarget_la_SOURCES += \
%D%/algorithm.h \
@@ -228,7 +229,8 @@ ESIRISC_SRC = \
%D%/arm_cti.h \
%D%/esirisc.h \
%D%/esirisc_jtag.h \
- %D%/esirisc_regs.h
+ %D%/esirisc_regs.h \
+ %D%/esirisc_trace.h
include %D%/openrisc/Makefile.am
include %D%/riscv/Makefile.am