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authorpierre Kuo <vichy.kuo@gmail.com>2015-02-13 11:27:52 +0800
committerPaul Fertser <fercerpav@gmail.com>2015-03-09 06:35:21 +0000
commit5e005f412962549916927d043946e6d3f506405a (patch)
tree084f1672c1f8245341e5779d15efe30f6844b200 /src/jtag
parente00a56bede4308426d17fda8cafacf7ddc82a238 (diff)
target/arm_disassembler: add exception related disassembly
Add ERET/HVC/SMC disassebly decoding flow, below is testing result > mdw 0x5c 4 0x0000005c: e160006e e1400072 e1600073 ee110f10 > arm disassemble 0x5c 4 0x0000005c 0xe160006e ERET 0x00000060 0xe1400072 HVC 0x0002 0x00000064 0xe1600073 SMC 0x0003 0x00000068 0xee110f10 MRC p15, 0x00, r0, c1, c0, 0x00 > Change-Id: I1beccff885b5b37747edd0b2e9fb2297ce466a00 Signed-off-by: pierre Kuo <vichy.kuo@gmail.com> Reviewed-on: http://openocd.zylin.com/2548 Tested-by: jenkins Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
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