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authorSpencer Oliver <spen@spen-soft.co.uk>2012-01-19 10:06:37 +0000
committerSpencer Oliver <spen@spen-soft.co.uk>2012-01-23 11:38:26 +0000
commit3a550e5b5fe011e526b150a5d234b48e8e2aaad6 (patch)
tree580b224fcee5ebf6001246e19850384390c8dfde /src/flash
parent9db465810a43e934f4f3c267ac279140c7c156dd (diff)
cleanup: rename armv4_5 to arm for readability
Nothing more than a name change, just to make reading the code a bit simpler. Change-Id: I73a16b7302b48ce07d9688162955aae71d11eb45 Signed-off-by: Spencer Oliver <spen@spen-soft.co.uk> Reviewed-on: http://openocd.zylin.com/390 Tested-by: jenkins Reviewed-by: Øyvind Harboe <oyvindharboe@gmail.com>
Diffstat (limited to 'src/flash')
-rw-r--r--src/flash/nand/arm_io.c8
-rw-r--r--src/flash/nor/str9xpec.c6
2 files changed, 7 insertions, 7 deletions
diff --git a/src/flash/nand/arm_io.c b/src/flash/nand/arm_io.c
index 7a6ceb39..431ac908 100644
--- a/src/flash/nand/arm_io.c
+++ b/src/flash/nand/arm_io.c
@@ -97,7 +97,7 @@ int arm_nandwrite(struct arm_nand_data *nand, uint8_t *data, int size)
{
struct target *target = nand->target;
struct arm_algorithm algo;
- struct arm *armv4_5 = target->arch_info;
+ struct arm *arm = target->arch_info;
struct reg_param reg_params[3];
uint32_t target_buf;
uint32_t exit_var = 0;
@@ -152,7 +152,7 @@ int arm_nandwrite(struct arm_nand_data *nand, uint8_t *data, int size)
buf_set_u32(reg_params[2].value, 0, 32, size);
/* armv4 must exit using a hardware breakpoint */
- if (armv4_5->is_armv4)
+ if (arm->is_armv4)
exit_var = nand->copy_area->address + sizeof(code) - 4;
/* use alg to write data from work area to NAND chip */
@@ -181,7 +181,7 @@ int arm_nandread(struct arm_nand_data *nand, uint8_t *data, uint32_t size)
{
struct target *target = nand->target;
struct arm_algorithm algo;
- struct arm *armv4_5 = target->arch_info;
+ struct arm *arm = target->arch_info;
struct reg_param reg_params[3];
uint32_t target_buf;
uint32_t exit_var = 0;
@@ -228,7 +228,7 @@ int arm_nandread(struct arm_nand_data *nand, uint8_t *data, uint32_t size)
buf_set_u32(reg_params[2].value, 0, 32, size);
/* armv4 must exit using a hardware breakpoint */
- if (armv4_5->is_armv4)
+ if (arm->is_armv4)
exit_var = nand->copy_area->address + sizeof(code) - 4;
/* use alg to write data from NAND chip to work area */
diff --git a/src/flash/nor/str9xpec.c b/src/flash/nor/str9xpec.c
index fc2ed359..b598c262 100644
--- a/src/flash/nor/str9xpec.c
+++ b/src/flash/nor/str9xpec.c
@@ -286,7 +286,7 @@ static int str9xpec_build_block_list(struct flash_bank *bank)
FLASH_BANK_COMMAND_HANDLER(str9xpec_flash_bank_command)
{
struct str9xpec_flash_controller *str9xpec_info;
- struct arm *armv4_5 = NULL;
+ struct arm *arm = NULL;
struct arm7_9_common *arm7_9 = NULL;
struct arm_jtag *jtag_info = NULL;
@@ -301,8 +301,8 @@ FLASH_BANK_COMMAND_HANDLER(str9xpec_flash_bank_command)
/* REVISIT verify that the jtag position of flash controller is
* right after *THIS* core, which must be a STR9xx core ...
*/
- armv4_5 = bank->target->arch_info;
- arm7_9 = armv4_5->arch_info;
+ arm = bank->target->arch_info;
+ arm7_9 = arm->arch_info;
jtag_info = &arm7_9->jtag_info;
/* The core is the next tap after the flash controller in the chain */