diff options
author | Tim Newsome <tim@sifive.com> | 2019-02-15 12:08:51 -0800 |
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committer | Matthias Welwarsky <matthias@welwarsky.de> | 2019-03-27 08:53:09 +0000 |
commit | bc72695f6738951571502706bd48680de5ccc84c (patch) | |
tree | 66a66342d6b3bd1f38dc33facb7ab1e433309236 /src/flash/nor/core.c | |
parent | 89f07325f2e7ca9d28ba0c54a26e3aab8b34984a (diff) |
Lots of RISC-V improvements.
This represents months of continuing RISC-V work, with too many changes
to list individually. Some improvements:
* Fixed memory leaks.
* Better handling of dbus timeouts.
* Add `riscv expose_custom` command.
* Somewhat deal with cache coherency.
* Deal with more timeouts during block memory accesses.
* Basic debug compliance test.
* Tell gdb which watchpoint hit.
* SMP support for use with -rtos hwthread
* Add `riscv set_ir`
Change-Id: Ica507ee2a57eaf51b578ab1d9b7de71512fdf47f
Signed-off-by: Tim Newsome <tim@sifive.com>
Reviewed-on: http://openocd.zylin.com/4922
Tested-by: jenkins
Reviewed-by: Philipp Guehring <pg@futureware.at>
Reviewed-by: Liviu Ionescu <ilg@livius.net>
Reviewed-by: Matthias Welwarsky <matthias@welwarsky.de>
Diffstat (limited to 'src/flash/nor/core.c')
0 files changed, 0 insertions, 0 deletions