build: use generic name for arm_algorithm vars

This makes the code a bit easier to read as arm_algorithm can
refer to other arch's, not just armv4_5.

Change-Id: I78c99d40f34cda04e06f2daee75b48ff40a1d23d
Signed-off-by: Spencer Oliver <spen@spen-soft.co.uk>
Reviewed-on: http://openocd.zylin.com/613
Tested-by: jenkins
Reviewed-by: Aurelien Jacobs <aurel@gnuage.org>
Reviewed-by: Freddie Chopin <freddie.chopin@gmail.com>

1 files changed, 19 insertions, 19 deletions

diff --git a/src/flash/nor/cfi.c b/src/flash/nor/cfi.c
index 0d8c694e..398dd61a 100644
--- a/src/flash/nor/cfi.c
+++ b/src/flash/nor/cfi.c
@@ -1146,7 +1146,7 @@ static int cfi_intel_write_block(struct flash_bank *bank, uint8_t *buffer,
 	struct cfi_flash_bank *cfi_info = bank->driver_priv;
 	struct target *target = bank->target;
 	struct reg_param reg_params[7];
-	struct arm_algorithm armv4_5_info;
+	struct arm_algorithm arm_algo;
 	struct working_area *source = NULL;
 	uint32_t buffer_size = 32768;
 	uint32_t write_command_val, busy_pattern_val, error_pattern_val;
@@ -1228,9 +1228,9 @@ static int cfi_intel_write_block(struct flash_bank *bank, uint8_t *buffer,
 
 	cfi_intel_clear_status_register(bank);
 
-	armv4_5_info.common_magic = ARM_COMMON_MAGIC;
-	armv4_5_info.core_mode = ARM_MODE_SVC;
-	armv4_5_info.core_state = ARM_STATE_ARM;
+	arm_algo.common_magic = ARM_COMMON_MAGIC;
+	arm_algo.core_mode = ARM_MODE_SVC;
+	arm_algo.core_state = ARM_STATE_ARM;
 
 	/* If we are setting up the write_algorith, we need target_code_src
 	 * if not we only need target_code_size. */
@@ -1344,7 +1344,7 @@ static int cfi_intel_write_block(struct flash_bank *bank, uint8_t *buffer,
 				cfi_info->write_algorithm->address + target_code_size -
 				sizeof(uint32_t),
 				10000,	/* 10s should be enough for max. 32k of data */
-				&armv4_5_info);
+				&arm_algo);
 
 		/* On failure try a fall back to direct word writes */
 		if (retval != ERROR_OK) {
@@ -1634,7 +1634,7 @@ static int cfi_spansion_write_block(struct flash_bank *bank, uint8_t *buffer,
 	struct cfi_spansion_pri_ext *pri_ext = cfi_info->pri_ext;
 	struct target *target = bank->target;
 	struct reg_param reg_params[10];
-	struct arm_algorithm armv4_5_info;
+	struct arm_algorithm arm_algo;
 	struct working_area *source;
 	uint32_t buffer_size = 32768;
 	uint32_t status;
@@ -1814,16 +1814,16 @@ static int cfi_spansion_write_block(struct flash_bank *bank, uint8_t *buffer,
 		return cfi_spansion_write_block_mips(bank, buffer, address, count);
 
 	if (is_armv7m(target_to_armv7m(target))) {	/* Cortex-M3 target */
-		armv4_5_info.common_magic = ARMV7M_COMMON_MAGIC;
-		armv4_5_info.core_mode = ARMV7M_MODE_HANDLER;
-		armv4_5_info.core_state = ARM_STATE_ARM;
+		arm_algo.common_magic = ARMV7M_COMMON_MAGIC;
+		arm_algo.core_mode = ARMV7M_MODE_HANDLER;
+		arm_algo.core_state = ARM_STATE_ARM;
 	} else if (is_arm7_9(target_to_arm7_9(target))) {
 		/* All other ARM CPUs have 32 bit instructions */
-		armv4_5_info.common_magic = ARM_COMMON_MAGIC;
-		armv4_5_info.core_mode = ARM_MODE_SVC;
-		armv4_5_info.core_state = ARM_STATE_ARM;
+		arm_algo.common_magic = ARM_COMMON_MAGIC;
+		arm_algo.core_mode = ARM_MODE_SVC;
+		arm_algo.core_state = ARM_STATE_ARM;
 	} else {
-		LOG_ERROR("Unknown ARM architecture");
+		LOG_ERROR("Unknown architecture");
 		return ERROR_FAIL;
 	}
 
@@ -1832,7 +1832,7 @@ static int cfi_spansion_write_block(struct flash_bank *bank, uint8_t *buffer,
 
 	switch (bank->bus_width) {
 		case 1:
-			if (armv4_5_info.common_magic != ARM_COMMON_MAGIC) {
+			if (arm_algo.common_magic != ARM_COMMON_MAGIC) {
 				LOG_ERROR("Unknown ARM architecture");
 				return ERROR_FAIL;
 			}
@@ -1842,10 +1842,10 @@ static int cfi_spansion_write_block(struct flash_bank *bank, uint8_t *buffer,
 		case 2:
 			/* Check for DQ5 support */
 			if (cfi_info->status_poll_mask & (1 << 5)) {
-				if (armv4_5_info.common_magic == ARM_COMMON_MAGIC) {/* armv4_5 target */
+				if (arm_algo.common_magic == ARM_COMMON_MAGIC) {/* armv4_5 target */
 					target_code_src = armv4_5_word_16_code;
 					target_code_size = sizeof(armv4_5_word_16_code);
-				} else if (armv4_5_info.common_magic == ARMV7M_COMMON_MAGIC) {	/*
+				} else if (arm_algo.common_magic == ARMV7M_COMMON_MAGIC) {	/*
 												 *cortex-m3
 												 *target
 												 **/
@@ -1854,7 +1854,7 @@ static int cfi_spansion_write_block(struct flash_bank *bank, uint8_t *buffer,
 				}
 			} else {
 				/* No DQ5 support. Use DQ7 DATA# polling only. */
-				if (armv4_5_info.common_magic != ARM_COMMON_MAGIC) {
+				if (arm_algo.common_magic != ARM_COMMON_MAGIC) {
 					LOG_ERROR("Unknown ARM architecture");
 					return ERROR_FAIL;
 				}
@@ -1863,7 +1863,7 @@ static int cfi_spansion_write_block(struct flash_bank *bank, uint8_t *buffer,
 			}
 			break;
 		case 4:
-			if (armv4_5_info.common_magic != ARM_COMMON_MAGIC) {
+			if (arm_algo.common_magic != ARM_COMMON_MAGIC) {
 				LOG_ERROR("Unknown ARM architecture");
 				return ERROR_FAIL;
 			}
@@ -1954,7 +1954,7 @@ static int cfi_spansion_write_block(struct flash_bank *bank, uint8_t *buffer,
 		retval = target_run_algorithm(target, 0, NULL, 10, reg_params,
 				cfi_info->write_algorithm->address,
 				cfi_info->write_algorithm->address + ((target_code_size) - 4),
-				10000, &armv4_5_info);
+				10000, &arm_algo);
 		if (retval != ERROR_OK)
 			break;