jtag ftdi: sample TDO on falling edge of TCK

Due to signal propagation delays, sampling TDO on rising TCK can become
quite peculiar at fast TCK rates. However, FTDI chips offer a possiblity
to sample TDO on falling edge. With this change, stable operation can be
achieved at 30MHz clock even over 10cm ribbon cable.

Change-Id: Icaf240535dae15512e3c60a944e22a5fbc1b0b06
Signed-off-by: Matthias Welwarsky <matthias@welwarsky.de>
Reviewed-on: http://openocd.zylin.com/3180
Tested-by: jenkins
Reviewed-by: Paul Fertser <fercerpav@gmail.com>

1 files changed, 14 insertions, 0 deletions

diff --git a/doc/openocd.texi b/doc/openocd.texi
index 78298b86..2e451140 100644
--- a/doc/openocd.texi
+++ b/doc/openocd.texi
@@ -2610,8 +2610,22 @@ Set a previously defined signal to the specified level.
 @end itemize
 @end deffn
 
+@deffn {Command} {ftdi_tdo_sample_edge} @option{rising}|@option{falling}
+Configure TCK edge at which the adapter samples the value of the TDO signal
+
+Due to signal propagation delays, sampling TDO on rising TCK can become quite
+peculiar at high JTAG clock speeds. However, FTDI chips offer a possiblity to sample
+TDO on falling edge of TCK. With some board/adapter configurations, this may increase
+stability at higher JTAG clocks.
+@itemize @minus
+@item @option{rising}, sample TDO on rising edge of TCK - this is the default
+@item @option{falling}, sample TDO on falling edge of TCK
+@end itemize
+@end deffn
+
 For example adapter definitions, see the configuration files shipped in the
 @file{interface/ftdi} directory.
+
 @end deffn
 
 @deffn {Interface Driver} {remote_bitbang}