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authorMatthias Welwarsky <matthias.welwarsky@sysgo.com>2018-04-05 13:42:21 +0200
committerMatthias Welwarsky <matthias@welwarsky.de>2019-03-04 11:53:00 +0000
commitdb429c34d047ac40dadf0087f3b3434551c855d4 (patch)
tree75b8c06d64c3f9decec08aa9583195c8fb04e100 /doc
parent21687eb983a4d5e30cd9c4050b9ebce2f3b280c7 (diff)
armv8: allow halt on exception
add command 'catch_exc' to halt a core on entering any of Secure EL1 or EL3 or Non-Secure EL1 or EL2. Change-Id: I0c68e247af68dd96616855a9bc1063c277d222e5 Signed-off-by: Matthias Welwarsky <matthias.welwarsky@sysgo.com> Reviewed-on: http://openocd.zylin.com/4479 Tested-by: jenkins Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com> Reviewed-by: Matthias Welwarsky <matthias@welwarsky.de>
Diffstat (limited to 'doc')
-rw-r--r--doc/openocd.texi8
1 files changed, 8 insertions, 0 deletions
diff --git a/doc/openocd.texi b/doc/openocd.texi
index 8b03b80b..2e04182b 100644
--- a/doc/openocd.texi
+++ b/doc/openocd.texi
@@ -9345,6 +9345,14 @@ be copied to an in-memory buffer identified by the @option{address} and
@option{size} options using DMA.
@end deffn
+@deffn Command {$target_name catch_exc} [@option{off}|@option{sec_el1}|@option{sec_el3}|@option{nsec_el1}|@option{nsec_el2}]+
+Cause @command{$target_name} to halt when an exception is taken. Any combination of
+Secure (sec) EL1/EL3 or Non-Secure (nsec) EL1/EL2 is valid. The target
+@command{$target_name} will halt before taking the exception. In order to resume
+the target, the exception catch must be disabled again with @command{$target_name catch_exc off}.
+Issuing the command without options prints the current configuration.
+@end deffn
+
@section Intel Architecture
Intel Quark X10xx is the first product in the Quark family of SoCs. It is an IA-32