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authorAndreas Färber <afaerber@suse.de>2016-04-30 15:10:05 +0200
committerTomas Vanek <vanekt@fbl.cz>2018-06-06 15:48:33 +0100
commit2d5f2ede55150235352773a976166c3ab68297bc (patch)
tree0b0799438322d99771c5c889c110716ef0067d7f /doc
parentd02de3a8a92091b9761ebaf44dff1a71f5b2edcb (diff)
flash/nor: Add PSoC 5LP flash driver
Always probe for ECC mode and display ECC sectors if disabled. Non-ECC write is implemented as zeroing the ECC/config bytes. Erasing ECC sectors is ignored, erase-checking takes them into account. Tested with CY8CKIT-059 (CY8C5888), except ECC mode. Change-Id: If63b9ffca7ad8de038be3c086c49712b629ec554 Signed-off-by: Andreas Färber <afaerber@suse.de> Signed-off-by: Tomas Vanek <vanekt@fbl.cz> Signed-off-by: Forest Crossman <cyrozap@gmail.com> Reviewed-on: http://openocd.zylin.com/3432 Tested-by: jenkins
Diffstat (limited to 'doc')
-rw-r--r--doc/openocd.texi26
1 files changed, 26 insertions, 0 deletions
diff --git a/doc/openocd.texi b/doc/openocd.texi
index 5b7d6d59..5c828383 100644
--- a/doc/openocd.texi
+++ b/doc/openocd.texi
@@ -6142,6 +6142,32 @@ The @var{num} parameter is a value shown by @command{flash banks}.
@end deffn
@end deffn
+@deffn {Flash Driver} psoc5lp
+All members of the PSoC 5LP microcontroller family from Cypress
+include internal program flash and use ARM Cortex-M3 cores.
+The driver probes for a number of these chips and autoconfigures itself,
+apart from the base address.
+
+@example
+flash bank $_FLASHNAME psoc5lp 0x00000000 0 0 0 $_TARGETNAME
+@end example
+
+@b{Note:} PSoC 5LP chips can be configured to have ECC enabled or disabled.
+@quotation Attention
+If flash operations are performed in ECC-disabled mode, they will also affect
+the ECC flash region. Erasing a 16k flash sector in the 0x00000000 area will
+then also erase the corresponding 2k data bytes in the 0x48000000 area.
+Writing to the ECC data bytes in ECC-disabled mode is not implemented.
+@end quotation
+
+Commands defined in the @var{psoc5lp} driver:
+
+@deffn Command {psoc5lp mass_erase}
+Erases all flash data and ECC/configuration bytes, all flash protection rows,
+and all row latches in all flash arrays on the device.
+@end deffn
+@end deffn
+
@deffn {Flash Driver} psoc6
Supports PSoC6 (CY8C6xxx) family of Cypress microcontrollers.
PSoC6 is a dual-core device with CM0+ and CM4 cores. Both cores share