Flash driver for STM32G0xx and STM32G4xx

Flash module of STM32G0/G4 family is quite similar to the one of
STM32L4, so only minor changes are required, in particular
adaption of flash loader to Cortex-M0. Register addresses
passed to flash loader to simplify integration of L5.
Added re-probe after option byte load.
Added flash size override via cfg file.
WRPxxR mask now based on max. number of pages instead of fixed 0xFF,
as G4 devices fill up unused bits with '1'.
Sizes in stm32l4_probe changed to multiples of 1kB.

Tested with Nucleo-G071RB, G030J6, Nucleo-G431RB and Nucleo-G474RE.
Gap handling in G4 Cat. 3 dual bank mode tested with STM32G473RB.
This handling isn't optimal as the bank size includes the
size of the gap. WB not tested.

Change-Id: I24df7c065afeb71c11c7e96de4aa9fdb91845593
Signed-off-by: Andreas Bolsch <hyphen0break@gmail.com>
Reviewed-on: http://openocd.zylin.com/4807
Tested-by: jenkins
Reviewed-by: Tarek BOCHKATI <tarek.bouchkati@gmail.com>
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>

2 files changed, 60 insertions, 46 deletions

diff --git a/contrib/loaders/flash/stm32/stm32l4x.S b/contrib/loaders/flash/stm32/stm32l4x.S
index e0ce3cb3..9e5c41eb 100644
--- a/contrib/loaders/flash/stm32/stm32l4x.S
+++ b/contrib/loaders/flash/stm32/stm32l4x.S
@@ -8,6 +8,9 @@
  *   Copyright (C) 2015 Uwe Bonnes                                         *
  *   bon@elektron.ikp.physik.tu-darmstadt.de                               *
  *                                                                         *
+ *   Copyright (C) 2018 Andreas Bolsch                                     *
+ *   andreas.bolsch@mni.thm.de                                             *
+ *                                                                         *
  *   This program is free software; you can redistribute it and/or modify  *
  *   it under the terms of the GNU General Public License as published by  *
  *   the Free Software Foundation; either version 2 of the License, or     *
@@ -25,68 +28,79 @@
 
 	.text
 	.syntax unified
-	.cpu cortex-m4
+	.cpu cortex-m0
 	.thumb
 
 /*
  * Params :
  * r0 = workarea start, status (out)
- * r1 = workarea end
+ * r1 = workarea end + 1
  * r2 = target address
  * r3 = count (64bit words)
- * r4 = flash base
+ * r4 = flash status register
+ * r5 = flash control register
  *
  * Clobbered:
- * r5   - rp
  * r6/7 - temp (64-bit)
- * r8   - wp, tmp
  */
 
-#define STM32_FLASH_CR_OFFSET	0x14	/* offset of CR register in FLASH struct */
-#define STM32_FLASH_SR_OFFSET	0x10	/* offset of SR register in FLASH struct */
-
-#define STM32_PROG	 0x1	/* PG */
+#include "../../../../src/flash/nor/stm32l4x.h"
 
 	.thumb_func
 	.global _start
+
 _start:
+	mov		r8, r3						/* copy dword count */
 wait_fifo:
-	ldr 	r8, [r0, #0]	/* read wp */
-	cmp 	r8, #0		/* abort if wp == 0 */
-	beq 	exit
-	ldr 	r5, [r0, #4]	/* read rp */
-	subs	r6, r8, r5	/* number of bytes available for read in r6*/
-	itt 	mi              /* if wrapped around*/
-	addmi	r6, r1          /* add size of buffer */
-	submi	r6, r0
-	cmp 	r6, #8		/* wait until 8 bytes are available */
-	bcc 	wait_fifo
+	ldr		r6, [r0, #0]				/* read wp */
+	cmp		r6, #0						/* if wp == 0,  */
+	beq		exit						/* then abort */
+	ldr		r3, [r0, #4]				/* read rp */
+	subs	r6, r6, r3					/* number of bytes available for read in r6 */
+	bpl		fifo_stat					/* if not wrapped around, skip */
+	adds	r6, r6, r1					/* add end of buffer */
+	subs	r6, r6, r0					/* sub start of buffer */
+fifo_stat:
+	cmp		r6, #8						/* wait until at least one dword available */
+	bcc		wait_fifo
 
-	ldr	r6, =STM32_PROG
-	str	r6, [r4, #STM32_FLASH_CR_OFFSET]
-	ldrd 	r6, [r5], #0x08	/* read one word from src, increment ptr */
-	strd 	r6, [r2], #0x08	/* write one word to dst, increment ptr */
+	movs	r6, #FLASH_PG				/* flash program enable */
+	str		r6, [r5]					/* write to FLASH_CR, start operation */
+	ldmia	r3!, {r6, r7}				/* read one dword from src, increment ptr */
+	stmia	r2!, {r6, r7}				/* write one dword to dst, increment ptr */
 	dsb
+	ldr		r7, =FLASH_BSY				/* FLASH_BSY mask */
 busy:
-	ldr 	r6, [r4, #STM32_FLASH_SR_OFFSET]
-	tst 	r6, #0x10000	/* BSY (bit16) == 1 => operation in progress */
-	bne 	busy		/* wait more... */
-	tst	r6, #0xfa	/* PGSERR | SIZERR | PGAERR | WRPERR | PROGERR | OPERR */
-	bne	error		/* fail... */
+	ldr 	r6, [r4]					/* get FLASH_SR register */
+	tst		r6, r7						/* BSY == 1 => operation in progress */
+	bne 	busy						/* if still set, wait more ... */
+	movs	r7, #FLASH_ERROR			/* all error bits */
+	tst		r6, r7						/* check for any error bit */
+	bne		error						/* fail ... */
+
+	cmp		r3, r1						/* rp at end of buffer? */
+	bcc		upd_rp						/* if no, then skip */
+	subs	r3, r3, r1					/* sub end of buffer */
+	adds	r3, r3, r0					/* add start of buffer */
+	adds	r3, r3, #8					/* skip wp and rp */
+upd_rp:
+	str		r3, [r0, #4]				/* store rp */
+	mov		r7, r8						/* get dword count */
+	subs	r7, r7, #1					/* decrement dword count */
+	mov		r8, r7						/* save dword count */
+	beq		exit						/* exit if done */
+	b		wait_fifo
+
+	.pool
 
-	cmp 	r5, r1		/* wrap rp at end of buffer */
-	it  	cs
-	addcs	r5, r0, #8	/* skip loader args */
-	str 	r5, [r0, #4]	/* store rp */
-	subs	r3, r3, #1	/* decrement dword count */
-	cbz 	r3, exit	/* loop if not done */
-	b	wait_fifo
 error:
-	movs	r1, #0
-	str	r1, [r0, #4]	/* set rp = 0 on error */
+	movs	r3, #0
+	str		r3, [r0, #4]				/* set rp = 0 on error */
 exit:
-	mov	r0, r6		/* return status in r0 */
+	mov		r0, r6						/* return status in r0 */
+	movs	r6, #0						/* flash program disable */
+	str		r6, [r5]					/* write to FLASH_CR */
+	movs	r6, #FLASH_ERROR			/* all error bits */
+	str		r6, [r4]					/* write to FLASH_CR to clear errors */
 	bkpt	#0x00
 
-	.pool
-
diff --git a/contrib/loaders/flash/stm32/stm32l4x.inc b/contrib/loaders/flash/stm32/stm32l4x.inc
index 4065d14e..df5c7edd 100644
--- a/contrib/loaders/flash/stm32/stm32l4x.inc
+++ b/contrib/loaders/flash/stm32/stm32l4x.inc
@@ -1,7 +1,7 @@
 /* Autogenerated with ../../../../src/helper/bin2char.sh */
-0xd0,0xf8,0x00,0x80,0xb8,0xf1,0x00,0x0f,0x20,0xd0,0x45,0x68,0xb8,0xeb,0x05,0x06,
-0x44,0xbf,0x76,0x18,0x36,0x1a,0x08,0x2e,0xf2,0xd3,0x0d,0x4e,0x66,0x61,0xf5,0xe8,
-0x02,0x67,0xe2,0xe8,0x02,0x67,0xbf,0xf3,0x4f,0x8f,0x26,0x69,0x16,0xf4,0x80,0x3f,
-0xfb,0xd1,0x16,0xf0,0xfa,0x0f,0x07,0xd1,0x8d,0x42,0x28,0xbf,0x00,0xf1,0x08,0x05,
-0x45,0x60,0x01,0x3b,0x13,0xb1,0xdb,0xe7,0x00,0x21,0x41,0x60,0x30,0x46,0x00,0xbe,
-0x01,0x00,0x00,0x00,
+0x98,0x46,0x06,0x68,0x00,0x2e,0x23,0xd0,0x43,0x68,0xf6,0x1a,0x01,0xd5,0x76,0x18,
+0x36,0x1a,0x08,0x2e,0xf5,0xd3,0x01,0x26,0x2e,0x60,0xc0,0xcb,0xc0,0xc2,0xbf,0xf3,
+0x4f,0x8f,0x09,0x4f,0x26,0x68,0x3e,0x42,0xfc,0xd1,0xfa,0x27,0x3e,0x42,0x0d,0xd1,
+0x8b,0x42,0x02,0xd3,0x5b,0x1a,0x1b,0x18,0x08,0x33,0x43,0x60,0x47,0x46,0x01,0x3f,
+0xb8,0x46,0x05,0xd0,0xdd,0xe7,0x00,0x00,0x00,0x00,0x01,0x00,0x00,0x23,0x43,0x60,
+0x30,0x46,0x00,0x26,0x2e,0x60,0xfa,0x26,0x26,0x60,0x00,0xbe,