diff options
| author | Radek Dostal <radek.dostal@streamunlimited.com> | 2015-05-21 18:12:39 +0200 |
|---|---|---|
| committer | Spencer Oliver <spen@spen-soft.co.uk> | 2015-08-06 13:07:49 +0100 |
| commit | 4517bcbd354206e2a9d132f80919617181059953 (patch) | |
| tree | 3722b6fe4111f74c487fe92b2566e7daedd39858 | |
| parent | 383a835bcd6ea6797fbf646a5faae3997b91c7e1 (diff) | |
tcl: replace $TARGETNAME with $_TARGETNAME
code polishing to be consistent with other scripts
Change-Id: Ib52a92f48df9d2bdf543792b856e33aa04dbebe3
Signed-off-by: Radek Dostal <radek.dostal@streamunlimited.com>
Reviewed-on: http://openocd.zylin.com/2779
Tested-by: jenkins
Reviewed-by: Spencer Oliver <spen@spen-soft.co.uk>
| -rw-r--r-- | tcl/board/tp-link_tl-mr3020.cfg | 4 | ||||
| -rw-r--r-- | tcl/target/ar71xx.cfg | 10 | ||||
| -rw-r--r-- | tcl/target/atheros_ar9331.cfg | 4 |
3 files changed, 9 insertions, 9 deletions
diff --git a/tcl/board/tp-link_tl-mr3020.cfg b/tcl/board/tp-link_tl-mr3020.cfg index 0498d60c..b7d8d5b6 100644 --- a/tcl/board/tp-link_tl-mr3020.cfg +++ b/tcl/board/tp-link_tl-mr3020.cfg @@ -34,11 +34,11 @@ proc ar9331_ddr1_init {} { ;# Each bit represents a cycle of valid data. } -$TARGETNAME configure -event reset-init { +$_TARGETNAME configure -event reset-init { ar9331_25mhz_pll_init sleep 1 ar9331_ddr1_init } set ram_boot_address 0xa0000000 -$TARGETNAME configure -work-area-phys 0xa1FFE000 -work-area-size 0x1000 +$_TARGETNAME configure -work-area-phys 0xa1FFE000 -work-area-size 0x1000 diff --git a/tcl/target/ar71xx.cfg b/tcl/target/ar71xx.cfg index 3ac61d94..196b0486 100644 --- a/tcl/target/ar71xx.cfg +++ b/tcl/target/ar71xx.cfg @@ -10,10 +10,10 @@ set CHIPNAME ar71xx jtag newtap $CHIPNAME cpu -irlen 5 -ircapture 0x1 -irmask 0x1f -expected-id 1 -set TARGETNAME $CHIPNAME.cpu -target create $TARGETNAME mips_m4k -endian big -chain-position $TARGETNAME +set _TARGETNAME $CHIPNAME.cpu +target create $_TARGETNAME mips_m4k -endian big -chain-position $_TARGETNAME -$TARGETNAME configure -event reset-halt-post { +$_TARGETNAME configure -event reset-halt-post { #setup PLL to lowest common denominator 300/300/150 setting mww 0xb8050000 0x000f40a3 ;# reset val + CPU:3 DDR:3 AHB:0 mww 0xb8050000 0x800f40a3 ;# send to PLL @@ -22,7 +22,7 @@ $TARGETNAME configure -event reset-halt-post { mww 0xb8050008 3 ;# set reset_switch and clock_switch (resets SoC) } -$TARGETNAME configure -event reset-init { +$_TARGETNAME configure -event reset-init { #complete pll initialization mww 0xb8050000 0x800f0080 ;# set sw_update bit mww 0xb8050008 0 ;# clear reset_switch bit @@ -50,7 +50,7 @@ $TARGETNAME configure -event reset-init { } # setup working area somewhere in RAM -$TARGETNAME configure -work-area-phys 0xa0600000 -work-area-size 0x20000 +$_TARGETNAME configure -work-area-phys 0xa0600000 -work-area-size 0x20000 # serial SPI capable flash # flash bank <driver> <base> <size> <chip_width> <bus_width> diff --git a/tcl/target/atheros_ar9331.cfg b/tcl/target/atheros_ar9331.cfg index 17503c78..c5609bb1 100644 --- a/tcl/target/atheros_ar9331.cfg +++ b/tcl/target/atheros_ar9331.cfg @@ -12,5 +12,5 @@ if { [info exists CPUTAPID] } { jtag newtap $_CHIPNAME cpu -irlen 5 -expected-id $_CPUTAPID -set TARGETNAME $_CHIPNAME.cpu -target create $TARGETNAME mips_m4k -endian big -chain-position $TARGETNAME +set _TARGETNAME $_CHIPNAME.cpu +target create $_TARGETNAME mips_m4k -endian big -chain-position $_TARGETNAME |