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-rw-r--r--toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99549.patch460
1 files changed, 460 insertions, 0 deletions
diff --git a/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99549.patch b/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99549.patch
new file mode 100644
index 0000000..4361702
--- /dev/null
+++ b/toolchain-layer/recipes-devtools/gcc/gcc-4.5/linaro/gcc-4.5-linaro-r99549.patch
@@ -0,0 +1,460 @@
+2011-10-03 Richard Sandiford <richard.sandiford@linaro.org>
+
+ gcc/
+ Backport from mainline:
+
+ 2010-12-06 Jakub Jelinek <jakub@redhat.com>
+
+ PR debug/46771
+ * reginfo.c (init_subregs_of_mode): Don't call find_subregs_of_mode
+ on DEBUG_INSNs.
+
+2011-10-03 Richard Sandiford <richard.sandiford@linaro.org>
+
+ gcc/
+ Backport from mainline:
+
+ 2011-09-22 Richard Sandiford <richard.sandiford@linaro.org>
+
+ * config/arm/predicates.md (expandable_comparison_operator): New
+ predicate, extracted from...
+ (arm_comparison_operator): ...here.
+ * config/arm/arm.md (cbranchsi4, cbranchsf4, cbranchdf4, cbranchdi4)
+ (cstoresi4, cstoresf4, cstoredf4, cstoredi4, movsicc, movsfcc)
+ (movdfcc): Use expandable_comparison_operator.
+
+ gcc/testsuite/
+ Backport from mainline:
+
+ 2011-09-22 Richard Sandiford <richard.sandiford@linaro.org>
+
+ * gcc.target/arm/cmp-1.c: New test.
+ * gcc.target/arm/cmp-2.c: Likewise.
+
+2011-10-03 Richard Sandiford <richard.sandiford@linaro.org>
+
+ gcc/
+ Backport from mainline:
+
+ 2011-09-07 Richard Sandiford <richard.sandiford@linaro.org>
+
+ PR target/49030
+ * config/arm/arm-protos.h (maybe_get_arm_condition_code): Declare.
+ * config/arm/arm.c (maybe_get_arm_condition_code): New function,
+ reusing the old code from get_arm_condition_code. Return ARM_NV
+ for invalid comparison codes.
+ (get_arm_condition_code): Redefine in terms of
+ maybe_get_arm_condition_code.
+ * config/arm/predicates.md (arm_comparison_operator): Use
+ maybe_get_arm_condition_code.
+
+ gcc/testsuite/
+ Backport from mainline:
+
+ 2011-09-07 Richard Sandiford <richard.sandiford@linaro.org>
+
+ PR target/49030
+ * gcc.dg/torture/pr49030.c: New test.
+
+=== modified file 'gcc/config/arm/arm-protos.h'
+--- old/gcc/config/arm/arm-protos.h 2011-09-15 10:06:35 +0000
++++ new/gcc/config/arm/arm-protos.h 2011-10-03 10:09:06 +0000
+@@ -182,6 +182,7 @@
+ #endif
+ extern int thumb_shiftable_const (unsigned HOST_WIDE_INT);
+ #ifdef RTX_CODE
++extern enum arm_cond_code maybe_get_arm_condition_code (rtx);
+ extern void thumb1_final_prescan_insn (rtx);
+ extern void thumb2_final_prescan_insn (rtx);
+ extern const char *thumb_load_double_from_address (rtx *);
+
+=== modified file 'gcc/config/arm/arm.c'
+--- old/gcc/config/arm/arm.c 2011-09-15 10:06:35 +0000
++++ new/gcc/config/arm/arm.c 2011-10-03 10:09:06 +0000
+@@ -17196,10 +17196,10 @@
+ decremented/zeroed by arm_asm_output_opcode as the insns are output. */
+
+ /* Returns the index of the ARM condition code string in
+- `arm_condition_codes'. COMPARISON should be an rtx like
+- `(eq (...) (...))'. */
+-static enum arm_cond_code
+-get_arm_condition_code (rtx comparison)
++ `arm_condition_codes', or ARM_NV if the comparison is invalid.
++ COMPARISON should be an rtx like `(eq (...) (...))'. */
++enum arm_cond_code
++maybe_get_arm_condition_code (rtx comparison)
+ {
+ enum machine_mode mode = GET_MODE (XEXP (comparison, 0));
+ enum arm_cond_code code;
+@@ -17223,11 +17223,11 @@
+ case CC_DLTUmode: code = ARM_CC;
+
+ dominance:
+- gcc_assert (comp_code == EQ || comp_code == NE);
+-
+ if (comp_code == EQ)
+ return ARM_INVERSE_CONDITION_CODE (code);
+- return code;
++ if (comp_code == NE)
++ return code;
++ return ARM_NV;
+
+ case CC_NOOVmode:
+ switch (comp_code)
+@@ -17236,7 +17236,7 @@
+ case EQ: return ARM_EQ;
+ case GE: return ARM_PL;
+ case LT: return ARM_MI;
+- default: gcc_unreachable ();
++ default: return ARM_NV;
+ }
+
+ case CC_Zmode:
+@@ -17244,7 +17244,7 @@
+ {
+ case NE: return ARM_NE;
+ case EQ: return ARM_EQ;
+- default: gcc_unreachable ();
++ default: return ARM_NV;
+ }
+
+ case CC_Nmode:
+@@ -17252,7 +17252,7 @@
+ {
+ case NE: return ARM_MI;
+ case EQ: return ARM_PL;
+- default: gcc_unreachable ();
++ default: return ARM_NV;
+ }
+
+ case CCFPEmode:
+@@ -17277,7 +17277,7 @@
+ /* UNEQ and LTGT do not have a representation. */
+ case UNEQ: /* Fall through. */
+ case LTGT: /* Fall through. */
+- default: gcc_unreachable ();
++ default: return ARM_NV;
+ }
+
+ case CC_SWPmode:
+@@ -17293,7 +17293,7 @@
+ case GTU: return ARM_CC;
+ case LEU: return ARM_CS;
+ case LTU: return ARM_HI;
+- default: gcc_unreachable ();
++ default: return ARM_NV;
+ }
+
+ case CC_Cmode:
+@@ -17301,7 +17301,7 @@
+ {
+ case LTU: return ARM_CS;
+ case GEU: return ARM_CC;
+- default: gcc_unreachable ();
++ default: return ARM_NV;
+ }
+
+ case CC_CZmode:
+@@ -17313,7 +17313,7 @@
+ case GTU: return ARM_HI;
+ case LEU: return ARM_LS;
+ case LTU: return ARM_CC;
+- default: gcc_unreachable ();
++ default: return ARM_NV;
+ }
+
+ case CC_NCVmode:
+@@ -17323,7 +17323,7 @@
+ case LT: return ARM_LT;
+ case GEU: return ARM_CS;
+ case LTU: return ARM_CC;
+- default: gcc_unreachable ();
++ default: return ARM_NV;
+ }
+
+ case CCmode:
+@@ -17339,13 +17339,22 @@
+ case GTU: return ARM_HI;
+ case LEU: return ARM_LS;
+ case LTU: return ARM_CC;
+- default: gcc_unreachable ();
++ default: return ARM_NV;
+ }
+
+ default: gcc_unreachable ();
+ }
+ }
+
++/* Like maybe_get_arm_condition_code, but never return ARM_NV. */
++static enum arm_cond_code
++get_arm_condition_code (rtx comparison)
++{
++ enum arm_cond_code code = maybe_get_arm_condition_code (comparison);
++ gcc_assert (code != ARM_NV);
++ return code;
++}
++
+ /* Tell arm_asm_output_opcode to output IT blocks for conditionally executed
+ instructions. */
+ void
+
+=== modified file 'gcc/config/arm/arm.md'
+--- old/gcc/config/arm/arm.md 2011-07-12 16:35:20 +0000
++++ new/gcc/config/arm/arm.md 2011-10-03 10:09:55 +0000
+@@ -6428,7 +6428,7 @@
+
+ (define_expand "cbranchsi4"
+ [(set (pc) (if_then_else
+- (match_operator 0 "arm_comparison_operator"
++ (match_operator 0 "expandable_comparison_operator"
+ [(match_operand:SI 1 "s_register_operand" "")
+ (match_operand:SI 2 "nonmemory_operand" "")])
+ (label_ref (match_operand 3 "" ""))
+@@ -6479,7 +6479,7 @@
+
+ (define_expand "cbranchsf4"
+ [(set (pc) (if_then_else
+- (match_operator 0 "arm_comparison_operator"
++ (match_operator 0 "expandable_comparison_operator"
+ [(match_operand:SF 1 "s_register_operand" "")
+ (match_operand:SF 2 "arm_float_compare_operand" "")])
+ (label_ref (match_operand 3 "" ""))
+@@ -6491,7 +6491,7 @@
+
+ (define_expand "cbranchdf4"
+ [(set (pc) (if_then_else
+- (match_operator 0 "arm_comparison_operator"
++ (match_operator 0 "expandable_comparison_operator"
+ [(match_operand:DF 1 "s_register_operand" "")
+ (match_operand:DF 2 "arm_float_compare_operand" "")])
+ (label_ref (match_operand 3 "" ""))
+@@ -6503,7 +6503,7 @@
+
+ (define_expand "cbranchdi4"
+ [(set (pc) (if_then_else
+- (match_operator 0 "arm_comparison_operator"
++ (match_operator 0 "expandable_comparison_operator"
+ [(match_operand:DI 1 "cmpdi_operand" "")
+ (match_operand:DI 2 "cmpdi_operand" "")])
+ (label_ref (match_operand 3 "" ""))
+@@ -7898,7 +7898,7 @@
+
+ (define_expand "cstoresi4"
+ [(set (match_operand:SI 0 "s_register_operand" "")
+- (match_operator:SI 1 "arm_comparison_operator"
++ (match_operator:SI 1 "expandable_comparison_operator"
+ [(match_operand:SI 2 "s_register_operand" "")
+ (match_operand:SI 3 "reg_or_int_operand" "")]))]
+ "TARGET_32BIT || TARGET_THUMB1"
+@@ -8034,7 +8034,7 @@
+
+ (define_expand "cstoresf4"
+ [(set (match_operand:SI 0 "s_register_operand" "")
+- (match_operator:SI 1 "arm_comparison_operator"
++ (match_operator:SI 1 "expandable_comparison_operator"
+ [(match_operand:SF 2 "s_register_operand" "")
+ (match_operand:SF 3 "arm_float_compare_operand" "")]))]
+ "TARGET_32BIT && TARGET_HARD_FLOAT"
+@@ -8044,7 +8044,7 @@
+
+ (define_expand "cstoredf4"
+ [(set (match_operand:SI 0 "s_register_operand" "")
+- (match_operator:SI 1 "arm_comparison_operator"
++ (match_operator:SI 1 "expandable_comparison_operator"
+ [(match_operand:DF 2 "s_register_operand" "")
+ (match_operand:DF 3 "arm_float_compare_operand" "")]))]
+ "TARGET_32BIT && TARGET_HARD_FLOAT && !TARGET_VFP_SINGLE"
+@@ -8054,7 +8054,7 @@
+
+ (define_expand "cstoredi4"
+ [(set (match_operand:SI 0 "s_register_operand" "")
+- (match_operator:SI 1 "arm_comparison_operator"
++ (match_operator:SI 1 "expandable_comparison_operator"
+ [(match_operand:DI 2 "cmpdi_operand" "")
+ (match_operand:DI 3 "cmpdi_operand" "")]))]
+ "TARGET_32BIT"
+@@ -8174,7 +8174,7 @@
+
+ (define_expand "movsicc"
+ [(set (match_operand:SI 0 "s_register_operand" "")
+- (if_then_else:SI (match_operand 1 "arm_comparison_operator" "")
++ (if_then_else:SI (match_operand 1 "expandable_comparison_operator" "")
+ (match_operand:SI 2 "arm_not_operand" "")
+ (match_operand:SI 3 "arm_not_operand" "")))]
+ "TARGET_32BIT"
+@@ -8194,7 +8194,7 @@
+
+ (define_expand "movsfcc"
+ [(set (match_operand:SF 0 "s_register_operand" "")
+- (if_then_else:SF (match_operand 1 "arm_comparison_operator" "")
++ (if_then_else:SF (match_operand 1 "expandable_comparison_operator" "")
+ (match_operand:SF 2 "s_register_operand" "")
+ (match_operand:SF 3 "nonmemory_operand" "")))]
+ "TARGET_32BIT && TARGET_HARD_FLOAT"
+@@ -8220,7 +8220,7 @@
+
+ (define_expand "movdfcc"
+ [(set (match_operand:DF 0 "s_register_operand" "")
+- (if_then_else:DF (match_operand 1 "arm_comparison_operator" "")
++ (if_then_else:DF (match_operand 1 "expandable_comparison_operator" "")
+ (match_operand:DF 2 "s_register_operand" "")
+ (match_operand:DF 3 "arm_float_add_operand" "")))]
+ "TARGET_32BIT && TARGET_HARD_FLOAT && (TARGET_FPA || TARGET_VFP_DOUBLE)"
+
+=== modified file 'gcc/config/arm/predicates.md'
+--- old/gcc/config/arm/predicates.md 2011-09-15 10:06:35 +0000
++++ new/gcc/config/arm/predicates.md 2011-10-03 10:09:55 +0000
+@@ -236,11 +236,15 @@
+
+ ;; True for integer comparisons and, if FP is active, for comparisons
+ ;; other than LTGT or UNEQ.
++(define_special_predicate "expandable_comparison_operator"
++ (match_code "eq,ne,le,lt,ge,gt,geu,gtu,leu,ltu,
++ unordered,ordered,unlt,unle,unge,ungt"))
++
++;; Likewise, but only accept comparisons that are directly supported
++;; by ARM condition codes.
+ (define_special_predicate "arm_comparison_operator"
+- (ior (match_code "eq,ne,le,lt,ge,gt,geu,gtu,leu,ltu")
+- (and (match_test "TARGET_32BIT && TARGET_HARD_FLOAT
+- && (TARGET_FPA || TARGET_VFP)")
+- (match_code "unordered,ordered,unlt,unle,unge,ungt"))))
++ (and (match_operand 0 "expandable_comparison_operator")
++ (match_test "maybe_get_arm_condition_code (op) != ARM_NV")))
+
+ (define_special_predicate "lt_ge_comparison_operator"
+ (match_code "lt,ge"))
+
+=== modified file 'gcc/reginfo.c'
+--- old/gcc/reginfo.c 2011-09-15 10:06:35 +0000
++++ new/gcc/reginfo.c 2011-10-03 10:10:17 +0000
+@@ -1350,7 +1350,7 @@
+
+ FOR_EACH_BB (bb)
+ FOR_BB_INSNS (bb, insn)
+- if (INSN_P (insn))
++ if (NONDEBUG_INSN_P (insn))
+ find_subregs_of_mode (PATTERN (insn));
+ }
+
+
+=== added file 'gcc/testsuite/gcc.dg/torture/pr49030.c'
+--- old/gcc/testsuite/gcc.dg/torture/pr49030.c 1970-01-01 00:00:00 +0000
++++ new/gcc/testsuite/gcc.dg/torture/pr49030.c 2011-10-03 10:09:06 +0000
+@@ -0,0 +1,19 @@
++void
++sample_move_d32u24_sS (char *dst, float *src, unsigned long nsamples,
++ unsigned long dst_skip)
++{
++ long long y;
++ while (nsamples--)
++ {
++ y = (long long) (*src * 8388608.0f) << 8;
++ if (y > 2147483647) {
++ *(int *) dst = 2147483647;
++ } else if (y < -2147483647 - 1) {
++ *(int *) dst = -2147483647 - 1;
++ } else {
++ *(int *) dst = (int) y;
++ }
++ dst += dst_skip;
++ src++;
++ }
++}
+
+=== added file 'gcc/testsuite/gcc.target/arm/cmp-1.c'
+--- old/gcc/testsuite/gcc.target/arm/cmp-1.c 1970-01-01 00:00:00 +0000
++++ new/gcc/testsuite/gcc.target/arm/cmp-1.c 2011-10-03 10:09:55 +0000
+@@ -0,0 +1,37 @@
++/* { dg-do compile } */
++/* { dg-options "-O" } */
++/* { dg-final { scan-assembler-not "\tbl\t" } } */
++/* { dg-final { scan-assembler-not "__aeabi" } } */
++int x, y;
++
++#define TEST_EXPR(NAME, ARGS, EXPR) \
++ int NAME##1 ARGS { return (EXPR); } \
++ int NAME##2 ARGS { return !(EXPR); } \
++ int NAME##3 ARGS { return (EXPR) ? x : y; } \
++ void NAME##4 ARGS { if (EXPR) x++; } \
++ void NAME##5 ARGS { if (!(EXPR)) x++; }
++
++#define TEST(NAME, TYPE, OPERATOR) \
++ TEST_EXPR (NAME##_rr, (TYPE a1, TYPE a2), a1 OPERATOR a2) \
++ TEST_EXPR (NAME##_rm, (TYPE a1, TYPE *a2), a1 OPERATOR *a2) \
++ TEST_EXPR (NAME##_mr, (TYPE *a1, TYPE a2), *a1 OPERATOR a2) \
++ TEST_EXPR (NAME##_mm, (TYPE *a1, TYPE *a2), *a1 OPERATOR *a2) \
++ TEST_EXPR (NAME##_rc, (TYPE a1), a1 OPERATOR 100) \
++ TEST_EXPR (NAME##_cr, (TYPE a1), 100 OPERATOR a1)
++
++#define TEST_OP(NAME, OPERATOR) \
++ TEST (sc_##NAME, signed char, OPERATOR) \
++ TEST (uc_##NAME, unsigned char, OPERATOR) \
++ TEST (ss_##NAME, short, OPERATOR) \
++ TEST (us_##NAME, unsigned short, OPERATOR) \
++ TEST (si_##NAME, int, OPERATOR) \
++ TEST (ui_##NAME, unsigned int, OPERATOR) \
++ TEST (sll_##NAME, long long, OPERATOR) \
++ TEST (ull_##NAME, unsigned long long, OPERATOR)
++
++TEST_OP (eq, ==)
++TEST_OP (ne, !=)
++TEST_OP (lt, <)
++TEST_OP (gt, >)
++TEST_OP (le, <=)
++TEST_OP (ge, >=)
+
+=== added file 'gcc/testsuite/gcc.target/arm/cmp-2.c'
+--- old/gcc/testsuite/gcc.target/arm/cmp-2.c 1970-01-01 00:00:00 +0000
++++ new/gcc/testsuite/gcc.target/arm/cmp-2.c 2011-10-03 10:09:55 +0000
+@@ -0,0 +1,49 @@
++/* { dg-do compile } */
++/* { dg-require-effective-target arm_vfp_ok } */
++/* { dg-skip-if "need fp instructions" { *-*-* } { "-mfloat-abi=soft" } { "" } } */
++/* { dg-options "-O -mfpu=vfp -mfloat-abi=softfp" } */
++/* { dg-final { scan-assembler-not "\tbl\t" } } */
++/* { dg-final { scan-assembler-not "__aeabi" } } */
++int x, y;
++
++#define EQ(X, Y) ((X) == (Y))
++#define NE(X, Y) ((X) != (Y))
++#define LT(X, Y) ((X) < (Y))
++#define GT(X, Y) ((X) > (Y))
++#define LE(X, Y) ((X) <= (Y))
++#define GE(X, Y) ((X) >= (Y))
++
++#define TEST_EXPR(NAME, ARGS, EXPR) \
++ int NAME##1 ARGS { return (EXPR); } \
++ int NAME##2 ARGS { return !(EXPR); } \
++ int NAME##3 ARGS { return (EXPR) ? x : y; } \
++ void NAME##4 ARGS { if (EXPR) x++; } \
++ void NAME##5 ARGS { if (!(EXPR)) x++; }
++
++#define TEST(NAME, TYPE, OPERATOR) \
++ TEST_EXPR (NAME##_rr, (TYPE a1, TYPE a2), OPERATOR (a1, a2)) \
++ TEST_EXPR (NAME##_rm, (TYPE a1, TYPE *a2), OPERATOR (a1, *a2)) \
++ TEST_EXPR (NAME##_mr, (TYPE *a1, TYPE a2), OPERATOR (*a1, a2)) \
++ TEST_EXPR (NAME##_mm, (TYPE *a1, TYPE *a2), OPERATOR (*a1, *a2)) \
++ TEST_EXPR (NAME##_rc, (TYPE a1), OPERATOR (a1, 100)) \
++ TEST_EXPR (NAME##_cr, (TYPE a1), OPERATOR (100, a1))
++
++#define TEST_OP(NAME, OPERATOR) \
++ TEST (f_##NAME, float, OPERATOR) \
++ TEST (d_##NAME, double, OPERATOR) \
++ TEST (ld_##NAME, long double, OPERATOR)
++
++TEST_OP (eq, EQ)
++TEST_OP (ne, NE)
++TEST_OP (lt, LT)
++TEST_OP (gt, GT)
++TEST_OP (le, LE)
++TEST_OP (ge, GE)
++TEST_OP (blt, __builtin_isless)
++TEST_OP (bgt, __builtin_isgreater)
++TEST_OP (ble, __builtin_islessequal)
++TEST_OP (bge, __builtin_isgreaterequal)
++/* This one should be expanded into separate ordered and equality
++ comparisons. */
++TEST_OP (blg, __builtin_islessgreater)
++TEST_OP (bun, __builtin_isunordered)
+
generated by cgit v1.2.3-18-g5258 (git 2.32.0) at 2024-11-21 23:35:39 +0000