aboutsummaryrefslogtreecommitdiff
path: root/test/CodeGen/CellSPU/loads.ll
blob: c46bcd18c15af5473f023130a71f0cf61c22cde2 (plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
; RUN: llc < %s -march=cellspu | FileCheck %s

; ModuleID = 'loads.bc'
target datalayout = "E-p:32:32:128-f64:64:128-f32:32:128-i64:32:128-i32:32:128-i16:16:128-i8:8:128-i1:8:128-a0:0:128-v128:128:128-s0:128:128"
target triple = "spu"

define <4 x float> @load_v4f32_1(<4 x float>* %a) nounwind readonly {
entry:
	%tmp1 = load <4 x float>* %a
	ret <4 x float> %tmp1
; CHECK:	lqd	$3, 0($3)
}

define <4 x float> @load_v4f32_2(<4 x float>* %a) nounwind readonly {
entry:
	%arrayidx = getelementptr <4 x float>* %a, i32 1
	%tmp1 = load <4 x float>* %arrayidx
	ret <4 x float> %tmp1
; CHECK:	lqd	$3, 16($3)
}


declare <4 x i32>* @getv4f32ptr()
define <4 x i32> @func() {
        ;CHECK: brasl
        ;CHECK: lr	{{\$[0-9]*, \$3}}
        ;CHECK: brasl
        %rv1 = call <4 x i32>* @getv4f32ptr()
        %rv2 = call <4 x i32>* @getv4f32ptr()
        %rv3 = load <4 x i32>* %rv1
        ret <4 x i32> %rv3
}

define <4 x float> @load_undef(){
	;CHECK lqd	$3, 0($3)
	%val = load <4 x float>* undef
	ret <4 x float> %val
}