path: root/lib/Target/SystemZ/SystemZInstrInfo.td

//===-- SystemZInstrInfo.td - General SystemZ instructions ----*- tblgen-*-===//
//
//                     The LLVM Compiler Infrastructure
//
// This file is distributed under the University of Illinois Open Source
// License. See LICENSE.TXT for details.
//
//===----------------------------------------------------------------------===//

//===----------------------------------------------------------------------===//
// Stack allocation
//===----------------------------------------------------------------------===//

def ADJCALLSTACKDOWN : Pseudo<(outs), (ins i64imm:$amt),
                              [(callseq_start timm:$amt)]>;
def ADJCALLSTACKUP   : Pseudo<(outs), (ins i64imm:$amt1, i64imm:$amt2),
                              [(callseq_end timm:$amt1, timm:$amt2)]>;

let neverHasSideEffects = 1 in {
  // Takes as input the value of the stack pointer after a dynamic allocation
  // has been made.  Sets the output to the address of the dynamically-
  // allocated area itself, skipping the outgoing arguments.
  //
  // This expands to an LA or LAY instruction.  We restrict the offset
  // to the range of LA and keep the LAY range in reserve for when
  // the size of the outgoing arguments is added.
  def ADJDYNALLOC : Pseudo<(outs GR64:$dst), (ins dynalloc12only:$src),
                           [(set GR64:$dst, dynalloc12only:$src)]>;
}

//===----------------------------------------------------------------------===//
// Control flow instructions
//===----------------------------------------------------------------------===//

// A return instruction.  R1 is the condition-code mask (all 1s)
// and R2 is the target address, which is always stored in %r14.
let isReturn = 1, isTerminator = 1, isBarrier = 1, hasCtrlDep = 1,
    R1 = 15, R2 = 14, isCodeGenOnly = 1 in {
  def RET : InstRR<0x07, (outs), (ins), "br\t%r14", [(z_retflag)]>;
}

// Unconditional branches.  R1 is the condition-code mask (all 1s).
let isBranch = 1, isTerminator = 1, isBarrier = 1, R1 = 15 in {
  let isIndirectBranch = 1 in
    def BR : InstRR<0x07, (outs), (ins ADDR64:$dst),
                    "br\t$dst", [(brind ADDR64:$dst)]>;

  // An assembler extended mnemonic for BRC.  Use a separate instruction for
  // the asm parser, so that we don't relax Js to external symbols into JGs.
  let isCodeGenOnly = 1 in
    def J : InstRI<0xA74, (outs), (ins brtarget16:$dst), "j\t$dst", []>;
  let isAsmParserOnly = 1 in
    def AsmJ : InstRI<0xA74, (outs), (ins brtarget16:$dst), "j\t$dst", []>;

  // An assembler extended mnemonic for BRCL.  (The extension is "G"
  // rather than "L" because "JL" is "Jump if Less".)
  def JG : InstRIL<0xC04, (outs), (ins brtarget32:$dst),
                   "jg\t$dst", [(br bb:$dst)]>;
}

// Conditional branches.  It's easier for LLVM to handle these branches
// in their raw BRC/BRCL form, with the 4-bit condition-code mask being
// the first operand.  It seems friendlier to use mnemonic forms like
// JE and JLH when writing out the assembly though.
multiclass CondBranches<Operand imm, string short, string long> {
  let isBranch = 1, isTerminator = 1, Uses = [PSW] in {
    def "" : InstRI<0xA74, (outs), (ins imm:$cond, brtarget16:$dst), short, []>;
    def L  : InstRIL<0xC04, (outs), (ins imm:$cond, brtarget32:$dst), long, []>;
  }
}
let isCodeGenOnly = 1 in
  defm BRC : CondBranches<cond4, "j$cond\t$dst", "jg$cond\t$dst">;
let isAsmParserOnly = 1 in
  defm AsmBRC : CondBranches<uimm8zx4, "brc\t$cond, $dst", "brcl\t$cond, $dst">;

def : Pat<(z_br_ccmask cond4:$cond, bb:$dst), (BRCL cond4:$cond, bb:$dst)>;

// Define AsmParser mnemonics for each condition code.
multiclass CondExtendedMnemonic<bits<4> Cond, string name> {
  let R1 = Cond in {
    def "" : InstRI<0xA74, (outs), (ins brtarget16:$dst),
                    "j"##name##"\t$dst", []>;
    def L  : InstRIL<0xC04, (outs), (ins brtarget32:$dst),
                    "jg"##name##"\t$dst", []>;
  }
}
let isAsmParserOnly = 1 in {
  defm AsmJO   : CondExtendedMnemonic<1,  "o">;
  defm AsmJH   : CondExtendedMnemonic<2,  "h">;
  defm AsmJNLE : CondExtendedMnemonic<3,  "nle">;
  defm AsmJL   : CondExtendedMnemonic<4,  "l">;
  defm AsmJNHE : CondExtendedMnemonic<5,  "nhe">;
  defm AsmJLH  : CondExtendedMnemonic<6,  "lh">;
  defm AsmJNE  : CondExtendedMnemonic<7,  "ne">;
  defm AsmJE   : CondExtendedMnemonic<8,  "e">;
  defm AsmJNLH : CondExtendedMnemonic<9,  "nlh">;
  defm AsmJHE  : CondExtendedMnemonic<10, "he">;
  defm AsmJNL  : CondExtendedMnemonic<11, "nl">;
  defm AsmJLE  : CondExtendedMnemonic<12, "le">;
  defm AsmJNH  : CondExtendedMnemonic<13, "nh">;
  defm AsmJNO  : CondExtendedMnemonic<14, "no">;
}

def Select32 : SelectWrapper<GR32>;
def Select64 : SelectWrapper<GR64>;

//===----------------------------------------------------------------------===//
// Call instructions
//===----------------------------------------------------------------------===//

// The definitions here are for the call-clobbered registers.
let isCall = 1, Defs = [R0D, R1D, R2D, R3D, R4D, R5D, R14D,
                        F0D, F1D, F2D, F3D, F4D, F5D, F6D, F7D],
    R1 = 14, isCodeGenOnly = 1 in {
  def BRAS  : InstRI<0xA75, (outs), (ins pcrel16call:$dst, variable_ops),
                     "bras\t%r14, $dst", []>;
  def BRASL : InstRIL<0xC05, (outs), (ins pcrel32call:$dst, variable_ops),
                      "brasl\t%r14, $dst", [(z_call pcrel32call:$dst)]>;
  def BASR  : InstRR<0x0D, (outs), (ins ADDR64:$dst, variable_ops),
                     "basr\t%r14, $dst", [(z_call ADDR64:$dst)]>;
}

// Define the general form of the call instructions for the asm parser.
// These instructions don't hard-code %r14 as the return address register.
let isAsmParserOnly = 1 in {
  def AsmBRAS  : InstRI<0xA75, (outs), (ins GR64:$save, brtarget16:$dst),
                        "bras\t$save, $dst", []>;
  def AsmBRASL : InstRIL<0xC05, (outs), (ins GR64:$save, brtarget32:$dst),
                        "brasl\t$save, $dst", []>;
  def AsmBASR  : InstRR<0x0D, (outs), (ins GR64:$save, ADDR64:$dst),
                        "basr\t$save, $dst", []>;
}

//===----------------------------------------------------------------------===//
// Move instructions
//===----------------------------------------------------------------------===//

// Register moves.
let neverHasSideEffects = 1 in {
  def LR  : UnaryRR <"lr",  0x18,   null_frag, GR32, GR32>;
  def LGR : UnaryRRE<"lgr", 0xB904, null_frag, GR64, GR64>;
}

// Immediate moves.
let neverHasSideEffects = 1, isAsCheapAsAMove = 1, isMoveImm = 1 in {
  // 16-bit sign-extended immediates.
  def LHI  : UnaryRI<"lhi",  0xA78, bitconvert, GR32, imm32sx16>;
  def LGHI : UnaryRI<"lghi", 0xA79, bitconvert, GR64, imm64sx16>;

  // Other 16-bit immediates.
  def LLILL : UnaryRI<"llill", 0xA5F, bitconvert, GR64, imm64ll16>;
  def LLILH : UnaryRI<"llilh", 0xA5E, bitconvert, GR64, imm64lh16>;
  def LLIHL : UnaryRI<"llihl", 0xA5D, bitconvert, GR64, imm64hl16>;
  def LLIHH : UnaryRI<"llihh", 0xA5C, bitconvert, GR64, imm64hh16>;

  // 32-bit immediates.
  def LGFI  : UnaryRIL<"lgfi",  0xC01, bitconvert, GR64, imm64sx32>;
  def LLILF : UnaryRIL<"llilf", 0xC0F, bitconvert, GR64, imm64lf32>;
  def LLIHF : UnaryRIL<"llihf", 0xC0E, bitconvert, GR64, imm64hf32>;
}

// Register loads.
let canFoldAsLoad = 1, SimpleBDXLoad = 1 in {
  defm L   : UnaryRXPair<"l", 0x58, 0xE358, load, GR32>;
  def  LRL : UnaryRILPC<"lrl", 0xC4D, aligned_load, GR32>;

  def LG   : UnaryRXY<"lg", 0xE304, load, GR64>;
  def LGRL : UnaryRILPC<"lgrl", 0xC48, aligned_load, GR64>;

  // These instructions are split after register allocation, so we don't
  // want a custom inserter.
  let Has20BitOffset = 1, HasIndex = 1, Is128Bit = 1 in {
    def L128 : Pseudo<(outs GR128:$dst), (ins bdxaddr20only128:$src),
                      [(set GR128:$dst, (load bdxaddr20only128:$src))]>;
  }
}

// Register stores.
let SimpleBDXStore = 1 in {
  let isCodeGenOnly = 1 in {
    defm ST32   : StoreRXPair<"st", 0x50, 0xE350, store, GR32>;
    def  STRL32 : StoreRILPC<"strl", 0xC4F, aligned_store, GR32>;
  }

  def STG   : StoreRXY<"stg", 0xE324, store, GR64>;
  def STGRL : StoreRILPC<"stgrl", 0xC4B, aligned_store, GR64>;

  // These instructions are split after register allocation, so we don't
  // want a custom inserter.
  let Has20BitOffset = 1, HasIndex = 1, Is128Bit = 1 in {
    def ST128 : Pseudo<(outs), (ins GR128:$src, bdxaddr20only128:$dst),
                       [(store GR128:$src, bdxaddr20only128:$dst)]>;
  }
}

// 8-bit immediate stores to 8-bit fields.
defm MVI : StoreSIPair<"mvi", 0x92, 0xEB52, truncstorei8, imm32zx8trunc>;

// 16-bit immediate stores to 16-, 32- or 64-bit fields.
def MVHHI : StoreSIL<"mvhhi", 0xE544, truncstorei16, imm32sx16trunc>;
def MVHI  : StoreSIL<"mvhi",  0xE54C, store,         imm32sx16>;
def MVGHI : StoreSIL<"mvghi", 0xE548, store,         imm64sx16>;

//===----------------------------------------------------------------------===//
// Sign extensions
//===----------------------------------------------------------------------===//

// 32-bit extensions from registers.
let neverHasSideEffects = 1 in {
  def LBR : UnaryRRE<"lbr", 0xB926, sext8,  GR32, GR32>;
  def LHR : UnaryRRE<"lhr", 0xB927, sext16, GR32, GR32>;
}

// 64-bit extensions from registers.
let neverHasSideEffects = 1 in {
  def LGBR : UnaryRRE<"lgbr", 0xB906, sext8,  GR64, GR64>;
  def LGHR : UnaryRRE<"lghr", 0xB907, sext16, GR64, GR64>;
  def LGFR : UnaryRRE<"lgfr", 0xB914, sext32, GR64, GR32>;
}

// Match 32-to-64-bit sign extensions in which the source is already
// in a 64-bit register.
def : Pat<(sext_inreg GR64:$src, i32),
          (LGFR (EXTRACT_SUBREG GR64:$src, subreg_32bit))>;

// 32-bit extensions from memory.
def  LB   : UnaryRXY<"lb", 0xE376, sextloadi8, GR32>;
defm LH   : UnaryRXPair<"lh", 0x48, 0xE378, sextloadi16, GR32>;
def  LHRL : UnaryRILPC<"lhrl", 0xC45, aligned_sextloadi16, GR32>;

// 64-bit extensions from memory.
def LGB   : UnaryRXY<"lgb", 0xE377, sextloadi8,  GR64>;
def LGH   : UnaryRXY<"lgh", 0xE315, sextloadi16, GR64>;
def LGF   : UnaryRXY<"lgf", 0xE314, sextloadi32, GR64>;
def LGHRL : UnaryRILPC<"lghrl", 0xC44, aligned_sextloadi16, GR64>;
def LGFRL : UnaryRILPC<"lgfrl", 0xC4C, aligned_sextloadi32, GR64>;

// If the sign of a load-extend operation doesn't matter, use the signed ones.
// There's not really much to choose between the sign and zero extensions,
// but LH is more compact than LLH for small offsets.
def : Pat<(i32 (extloadi8  bdxaddr20only:$src)), (LB  bdxaddr20only:$src)>;
def : Pat<(i32 (extloadi16 bdxaddr12pair:$src)), (LH  bdxaddr12pair:$src)>;
def : Pat<(i32 (extloadi16 bdxaddr20pair:$src)), (LHY bdxaddr20pair:$src)>;

def : Pat<(i64 (extloadi8  bdxaddr20only:$src)), (LGB bdxaddr20only:$src)>;
def : Pat<(i64 (extloadi16 bdxaddr20only:$src)), (LGH bdxaddr20only:$src)>;
def : Pat<(i64 (extloadi32 bdxaddr20only:$src)), (LGF bdxaddr20only:$src)>;

//===----------------------------------------------------------------------===//
// Zero extensions
//===----------------------------------------------------------------------===//

// 32-bit extensions from registers.
let neverHasSideEffects = 1 in {
  def LLCR : UnaryRRE<"llcr", 0xB994, zext8,  GR32, GR32>;
  def LLHR : UnaryRRE<"llhr", 0xB995, zext16, GR32, GR32>;
}

// 64-bit extensions from registers.
let neverHasSideEffects = 1 in {
  def LLGCR : UnaryRRE<"llgcr", 0xB984, zext8,  GR64, GR64>;
  def LLGHR : UnaryRRE<"llghr", 0xB985, zext16, GR64, GR64>;
  def LLGFR : UnaryRRE<"llgfr", 0xB916, zext32, GR64, GR32>;
}

// Match 32-to-64-bit zero extensions in which the source is already
// in a 64-bit register.
def : Pat<(and GR64:$src, 0xffffffff),
          (LLGFR (EXTRACT_SUBREG GR64:$src, subreg_32bit))>;

// 32-bit extensions from memory.
def LLC   : UnaryRXY<"llc", 0xE394, zextloadi8,  GR32>;
def LLH   : UnaryRXY<"llh", 0xE395, zextloadi16, GR32>;
def LLHRL : UnaryRILPC<"llhrl", 0xC42, aligned_zextloadi16, GR32>;

// 64-bit extensions from memory.
def LLGC   : UnaryRXY<"llgc", 0xE390, zextloadi8,  GR64>;
def LLGH   : UnaryRXY<"llgh", 0xE391, zextloadi16, GR64>;
def LLGF   : UnaryRXY<"llgf", 0xE316, zextloadi32, GR64>;
def LLGHRL : UnaryRILPC<"llghrl", 0xC46, aligned_zextloadi16, GR64>;
def LLGFRL : UnaryRILPC<"llgfrl", 0xC4E, aligned_zextloadi32, GR64>;

//===----------------------------------------------------------------------===//
// Truncations
//===----------------------------------------------------------------------===//

// Truncations of 64-bit registers to 32-bit registers.
def : Pat<(i32 (trunc GR64:$src)),
          (EXTRACT_SUBREG GR64:$src, subreg_32bit)>;

// Truncations of 32-bit registers to memory.
let isCodeGenOnly = 1 in {
  defm STC32   : StoreRXPair<"stc", 0x42, 0xE372, truncstorei8,  GR32>;
  defm STH32   : StoreRXPair<"sth", 0x40, 0xE370, truncstorei16, GR32>;
  def  STHRL32 : StoreRILPC<"sthrl", 0xC47, aligned_truncstorei16, GR32>;
}

// Truncations of 64-bit registers to memory.
defm STC   : StoreRXPair<"stc", 0x42, 0xE372, truncstorei8,  GR64>;
defm STH   : StoreRXPair<"sth", 0x40, 0xE370, truncstorei16, GR64>;
def  STHRL : StoreRILPC<"sthrl", 0xC47, aligned_truncstorei16, GR64>;
defm ST    : StoreRXPair<"st", 0x50, 0xE350, truncstorei32, GR64>;
def  STRL  : StoreRILPC<"strl", 0xC4F, aligned_truncstorei32, GR64>;

//===----------------------------------------------------------------------===//
// Multi-register moves
//===----------------------------------------------------------------------===//

// Multi-register loads.
def LMG : LoadMultipleRSY<"lmg", 0xEB04, GR64>;

// Multi-register stores.
def STMG : StoreMultipleRSY<"stmg", 0xEB24, GR64>;

//===----------------------------------------------------------------------===//
// Byte swaps
//===----------------------------------------------------------------------===//

// Byte-swapping register moves.
let neverHasSideEffects = 1 in {
  def LRVR  : UnaryRRE<"lrvr",  0xB91F, bswap, GR32, GR32>;
  def LRVGR : UnaryRRE<"lrvgr", 0xB90F, bswap, GR64, GR64>;
}

// Byte-swapping loads.
def LRV  : UnaryRXY<"lrv",  0xE31E, loadu<bswap>, GR32>;
def LRVG : UnaryRXY<"lrvg", 0xE30F, loadu<bswap>, GR64>;

// Byte-swapping stores.
def STRV  : StoreRXY<"strv",  0xE33E, storeu<bswap>, GR32>;
def STRVG : StoreRXY<"strvg", 0xE32F, storeu<bswap>, GR64>;

//===----------------------------------------------------------------------===//
// Load address instructions
//===----------------------------------------------------------------------===//

// Load BDX-style addresses.
let neverHasSideEffects = 1, Function = "la" in {
  let PairType = "12" in
    def LA : InstRX<0x41, (outs GR64:$dst), (ins laaddr12pair:$src),
                    "la\t$dst, $src",
                    [(set GR64:$dst, laaddr12pair:$src)]>;
  let PairType = "20" in
    def LAY : InstRXY<0xE371, (outs GR64:$dst), (ins laaddr20pair:$src),
                      "lay\t$dst, $src",
                      [(set GR64:$dst, laaddr20pair:$src)]>;
}

// Load a PC-relative address.  There's no version of this instruction
// with a 16-bit offset, so there's no relaxation.
let neverHasSideEffects = 1 in {
  def LARL : InstRIL<0xC00, (outs GR64:$dst), (ins pcrel32:$src),
                     "larl\t$dst, $src",
                     [(set GR64:$dst, pcrel32:$src)]>;
}

//===----------------------------------------------------------------------===//
// Negation
//===----------------------------------------------------------------------===//

let Defs = [PSW] in {
  def LCR   : UnaryRR <"lcr",   0x13,   ineg,      GR32, GR32>;
  def LCGR  : UnaryRRE<"lcgr",  0xB903, ineg,      GR64, GR64>;
  def LCGFR : UnaryRRE<"lcgfr", 0xB913, null_frag, GR64, GR32>;
}
defm : SXU<ineg, LCGFR>;

//===----------------------------------------------------------------------===//
// Insertion
//===----------------------------------------------------------------------===//

let isCodeGenOnly = 1 in
  defm IC32 : BinaryRXPair<"ic", 0x43, 0xE373, inserti8, GR32, zextloadi8>;
defm IC : BinaryRXPair<"ic", 0x43, 0xE373, inserti8, GR64, zextloadi8>;

defm : InsertMem<"inserti8", IC32,  GR32, zextloadi8, bdxaddr12pair>;
defm : InsertMem<"inserti8", IC32Y, GR32, zextloadi8, bdxaddr20pair>;

defm : InsertMem<"inserti8", IC,  GR64, zextloadi8, bdxaddr12pair>;
defm : InsertMem<"inserti8", ICY, GR64, zextloadi8, bdxaddr20pair>;

// Insertions of a 16-bit immediate, leaving other bits unaffected.
// We don't have or_as_insert equivalents of these operations because
// OI is available instead.
let isCodeGenOnly = 1 in {
  def IILL32 : BinaryRI<"iill", 0xA53, insertll, GR32, imm32ll16>;
  def IILH32 : BinaryRI<"iilh", 0xA52, insertlh, GR32, imm32lh16>;
}
def IILL : BinaryRI<"iill", 0xA53, insertll, GR64, imm64ll16>;
def IILH : BinaryRI<"iilh", 0xA52, insertlh, GR64, imm64lh16>;
def IIHL : BinaryRI<"iihl", 0xA51, inserthl, GR64, imm64hl16>;
def IIHH : BinaryRI<"iihh", 0xA50, inserthh, GR64, imm64hh16>;

// ...likewise for 32-bit immediates.  For GR32s this is a general
// full-width move.  (We use IILF rather than something like LLILF
// for 32-bit moves because IILF leaves the upper 32 bits of the
// GR64 unchanged.)
let isCodeGenOnly = 1 in {
  def IILF32 : UnaryRIL<"iilf", 0xC09, bitconvert, GR32, uimm32>;
}
def IILF : BinaryRIL<"iilf", 0xC09, insertlf, GR64, imm64lf32>;
def IIHF : BinaryRIL<"iihf", 0xC08, inserthf, GR64, imm64hf32>;

// An alternative model of inserthf, with the first operand being
// a zero-extended value.
def : Pat<(or (zext32 GR32:$src), imm64hf32:$imm),
          (IIHF (INSERT_SUBREG (i64 (IMPLICIT_DEF)), GR32:$src, subreg_32bit),
                imm64hf32:$imm)>;

//===----------------------------------------------------------------------===//
// Addition
//===----------------------------------------------------------------------===//

// Plain addition.
let Defs = [PSW] in {
  // Addition of a register.
  let isCommutable = 1 in {
    def AR  : BinaryRR <"ar",  0x1A,   add, GR32, GR32>;
    def AGR : BinaryRRE<"agr", 0xB908, add, GR64, GR64>;
  }
  def AGFR : BinaryRRE<"agfr", 0xB918, null_frag, GR64, GR32>;

  // Addition of signed 16-bit immediates.
  def AHI  : BinaryRI<"ahi",  0xA7A, add, GR32, imm32sx16>;
  def AGHI : BinaryRI<"aghi", 0xA7B, add, GR64, imm64sx16>;

  // Addition of signed 32-bit immediates.
  def AFI  : BinaryRIL<"afi",  0xC29, add, GR32, simm32>;
  def AGFI : BinaryRIL<"agfi", 0xC28, add, GR64, imm64sx32>;

  // Addition of memory.
  defm AH  : BinaryRXPair<"ah", 0x4A, 0xE37A, add, GR32, sextloadi16>;
  defm A   : BinaryRXPair<"a",  0x5A, 0xE35A, add, GR32, load>;
  def  AGF : BinaryRXY<"agf", 0xE318, add, GR64, sextloadi32>;
  def  AG  : BinaryRXY<"ag",  0xE308, add, GR64, load>;

  // Addition to memory.
  def ASI  : BinarySIY<"asi",  0xEB6A, add, imm32sx8>;
  def AGSI : BinarySIY<"agsi", 0xEB7A, add, imm64sx8>;
}
defm : SXB<add, GR64, AGFR>;

// Addition producing a carry.
let Defs = [PSW] in {
  // Addition of a register.
  let isCommutable = 1 in {
    def ALR  : BinaryRR <"alr",  0x1E,   addc, GR32, GR32>;
    def ALGR : BinaryRRE<"algr", 0xB90A, addc, GR64, GR64>;
  }
  def ALGFR : BinaryRRE<"algfr", 0xB91A, null_frag, GR64, GR32>;

  // Addition of unsigned 32-bit immediates.
  def ALFI  : BinaryRIL<"alfi",  0xC2B, addc, GR32, uimm32>;
  def ALGFI : BinaryRIL<"algfi", 0xC2A, addc, GR64, imm64zx32>;

  // Addition of memory.
  defm AL   : BinaryRXPair<"al", 0x5E, 0xE35E, addc, GR32, load>;
  def  ALGF : BinaryRXY<"algf", 0xE31A, addc, GR64, zextloadi32>;
  def  ALG  : BinaryRXY<"alg",  0xE30A, addc, GR64, load>;
}
defm : ZXB<addc, GR64, ALGFR>;

// Addition producing and using a carry.
let Defs = [PSW], Uses = [PSW] in {
  // Addition of a register.
  def ALCR  : BinaryRRE<"alcr",  0xB998, adde, GR32, GR32>;
  def ALCGR : BinaryRRE<"alcgr", 0xB988, adde, GR64, GR64>;

  // Addition of memory.
  def ALC  : BinaryRXY<"alc",  0xE398, adde, GR32, load>;
  def ALCG : BinaryRXY<"alcg", 0xE388, adde, GR64, load>;
}

//===----------------------------------------------------------------------===//
// Subtraction
//===----------------------------------------------------------------------===//

// Plain substraction.  Although immediate forms exist, we use the
// add-immediate instruction instead.
let Defs = [PSW] in {
  // Subtraction of a register.
  def SR   : BinaryRR <"sr",   0x1B,   sub,       GR32, GR32>;
  def SGFR : BinaryRRE<"sgfr", 0xB919, null_frag, GR64, GR32>;
  def SGR  : BinaryRRE<"sgr",  0xB909, sub,       GR64, GR64>;

  // Subtraction of memory.
  defm S   : BinaryRXPair<"s", 0x5B, 0xE35B, sub, GR32, load>;
  def  SGF : BinaryRXY<"sgf", 0xE319, sub, GR64, sextloadi32>;
  def  SG  : BinaryRXY<"sg",  0xE309, sub, GR64, load>;
}
defm : SXB<sub, GR64, SGFR>;

// Subtraction producing a carry.
let Defs = [PSW] in {
  // Subtraction of a register.
  def SLR   : BinaryRR <"slr",   0x1F,   subc,      GR32, GR32>;
  def SLGFR : BinaryRRE<"slgfr", 0xB91B, null_frag, GR64, GR32>;
  def SLGR  : BinaryRRE<"slgr",  0xB90B, subc,      GR64, GR64>;

  // Subtraction of unsigned 32-bit immediates.  These don't match
  // subc because we prefer addc for