path: root/lib/Target/SystemZ/SystemZISelDAGToDAG.cpp

//==-- SystemZISelDAGToDAG.cpp - A dag to dag inst selector for SystemZ ---===//
//
//                     The LLVM Compiler Infrastructure
//
// This file is distributed under the University of Illinois Open Source
// License. See LICENSE.TXT for details.
//
//===----------------------------------------------------------------------===//
//
// This file defines an instruction selector for the SystemZ target.
//
//===----------------------------------------------------------------------===//

#include "SystemZ.h"
#include "SystemZISelLowering.h"
#include "SystemZTargetMachine.h"
#include "llvm/DerivedTypes.h"
#include "llvm/Function.h"
#include "llvm/Intrinsics.h"
#include "llvm/CallingConv.h"
#include "llvm/Constants.h"
#include "llvm/CodeGen/MachineFrameInfo.h"
#include "llvm/CodeGen/MachineFunction.h"
#include "llvm/CodeGen/MachineInstrBuilder.h"
#include "llvm/CodeGen/MachineRegisterInfo.h"
#include "llvm/CodeGen/SelectionDAG.h"
#include "llvm/CodeGen/SelectionDAGISel.h"
#include "llvm/Target/TargetLowering.h"
#include "llvm/Support/Compiler.h"
#include "llvm/Support/Debug.h"
using namespace llvm;

namespace {
  /// SystemZRRIAddressMode - This corresponds to rriaddr, but uses SDValue's
  /// instead of register numbers for the leaves of the matched tree.
  struct SystemZRRIAddressMode {
    enum {
      RegBase,
      FrameIndexBase
    } BaseType;

    struct {            // This is really a union, discriminated by BaseType!
      SDValue Reg;
      int FrameIndex;
    } Base;

    SDValue IndexReg;
    int32_t Disp;

    SystemZRRIAddressMode()
      : BaseType(RegBase), IndexReg(), Disp(0) {
    }

    void dump() {
      cerr << "SystemZRRIAddressMode " << this << "\n";
      if (BaseType == RegBase) {
        cerr << "Base.Reg ";
        if (Base.Reg.getNode() != 0) Base.Reg.getNode()->dump();
        else cerr << "nul";
      } else {
        cerr << " Base.FrameIndex " << Base.FrameIndex << "\n";
      }
      cerr << "IndexReg ";
      if (IndexReg.getNode() != 0) IndexReg.getNode()->dump();
      else cerr << "nul";
      cerr << " Disp " << Disp << "\n";
    }
  };
}

/// SystemZDAGToDAGISel - SystemZ specific code to select SystemZ machine
/// instructions for SelectionDAG operations.
///
namespace {
  class SystemZDAGToDAGISel : public SelectionDAGISel {
    SystemZTargetLowering &Lowering;
    const SystemZSubtarget &Subtarget;

  public:
    SystemZDAGToDAGISel(SystemZTargetMachine &TM, CodeGenOpt::Level OptLevel)
      : SelectionDAGISel(TM, OptLevel),
        Lowering(*TM.getTargetLowering()),
        Subtarget(*TM.getSubtargetImpl()) { }

    virtual void InstructionSelect();

    virtual const char *getPassName() const {
      return "SystemZ DAG->DAG Pattern Instruction Selection";
    }

    /// getI16Imm - Return a target constant with the specified value, of type
    /// i16.
    inline SDValue getI16Imm(uint64_t Imm) {
      return CurDAG->getTargetConstant(Imm, MVT::i16);
    }

    /// getI32Imm - Return a target constant with the specified value, of type
    /// i32.
    inline SDValue getI32Imm(uint64_t Imm) {
      return CurDAG->getTargetConstant(Imm, MVT::i32);
    }

    // Include the pieces autogenerated from the target description.
    #include "SystemZGenDAGISel.inc"

  private:
    bool SelectAddrRRI(SDValue Op, SDValue Addr,
                       SDValue &Base, SDValue &Index, SDValue &Disp);
    SDNode *Select(SDValue Op);
    bool SelectAddrRI(const SDValue& Op, SDValue& Addr,
                      SDValue &Base, SDValue &Disp);
    bool MatchAddress(SDValue N, SystemZRRIAddressMode &AM, unsigned Depth = 0);
    bool MatchAddressBase(SDValue N, SystemZRRIAddressMode &AM);

  #ifndef NDEBUG
    unsigned Indent;
  #endif
  };
}  // end anonymous namespace

/// createSystemZISelDag - This pass converts a legalized DAG into a
/// SystemZ-specific DAG, ready for instruction scheduling.
///
FunctionPass *llvm::createSystemZISelDag(SystemZTargetMachine &TM,
                                        CodeGenOpt::Level OptLevel) {
  return new SystemZDAGToDAGISel(TM, OptLevel);
}

/// isImmSExt20 - This method tests to see if the node is either a 32-bit
/// or 64-bit immediate, and if the value can be accurately represented as a
/// sign extension from a 20-bit value. If so, this returns true and the
/// immediate.
static bool isImmSExt20(int64_t Val, int32_t &Imm) {
  if (Val >= -524288 && Val <= 524287) {
    Imm = (int32_t)Val;
    return true;
  }
  return false;
}

static bool isImmSExt20(SDNode *N, int32_t &Imm) {
  if (N->getOpcode() != ISD::Constant)
    return false;

  return isImmSExt20(cast<ConstantSDNode>(N)->getSExtValue(), Imm);
}

static bool isImmSExt20(SDValue Op, int32_t &Imm) {
  return isImmSExt20(Op.getNode(), Imm);
}

/// Returns true if the address can be represented by a base register plus
/// a signed 20-bit displacement [r+imm].
bool SystemZDAGToDAGISel::SelectAddrRI(const SDValue& Op, SDValue& Addr,
                                       SDValue &Base, SDValue &Disp) {
  // FIXME dl should come from parent load or store, not from address
  DebugLoc dl = Addr.getDebugLoc();
  MVT VT = Addr.getValueType();

  if (Addr.getOpcode() == ISD::ADD) {
    int32_t Imm = 0;
    if (isImmSExt20(Addr.getOperand(1), Imm)) {
      Disp = CurDAG->getTargetConstant(Imm, MVT::i32);
      if (FrameIndexSDNode *FI =
          dyn_cast<FrameIndexSDNode>(Addr.getOperand(0))) {
        Base = CurDAG->getTargetFrameIndex(FI->getIndex(), VT);
      } else {
        Base = Addr.getOperand(0);
      }
      return true; // [r+i]
    }
  } else if (Addr.getOpcode() == ISD::OR) {
    int32_t Imm = 0;
    if (isImmSExt20(Addr.getOperand(1), Imm)) {
      // If this is an or of disjoint bitfields, we can codegen this as an add
      // (for better address arithmetic) if the LHS and RHS of the OR are
      // provably disjoint.
      APInt LHSKnownZero, LHSKnownOne;
      CurDAG->ComputeMaskedBits(Addr.getOperand(0),
                                APInt::getAllOnesValue(Addr.getOperand(0)
                                                       .getValueSizeInBits()),
                                LHSKnownZero, LHSKnownOne);

      if ((LHSKnownZero.getZExtValue()|~(uint64_t)Imm) == ~0ULL) {
        // If all of the bits are known zero on the LHS or RHS, the add won't
        // carry.
        Base = Addr.getOperand(0);
        Disp = CurDAG->getTargetConstant(Imm, MVT::i32);
        return true;
      }
    }
  } else if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(Addr)) {
    // Loading from a constant address.

    // If this address fits entirely in a 20-bit sext immediate field, codegen
    // this as "d(r0)"
    int32_t Imm;
    if (isImmSExt20(CN, Imm)) {
      Disp = CurDAG->getTargetConstant(Imm, MVT::i32);
      Base = CurDAG->getRegister(0, VT);
      return true;
    }
  }

  Disp = CurDAG->getTargetConstant(0, MVT::i32);
  if (FrameIndexSDNode *FI = dyn_cast<FrameIndexSDNode>(Addr))
    Base = CurDAG->getTargetFrameIndex(FI->getIndex(), VT);
  else
    Base = Addr;
  return true;      // [r+0]
}

/// MatchAddress - Add the specified node to the specified addressing mode,
/// returning true if it cannot be done.  This just pattern matches for the
/// addressing mode.
bool SystemZDAGToDAGISel::MatchAddress(SDValue N, SystemZRRIAddressMode &AM,
                                       unsigned Depth) {
  DebugLoc dl = N.getDebugLoc();
  DOUT << "MatchAddress: "; DEBUG(AM.dump());
  // Limit recursion.
  if (Depth > 5)
    return MatchAddressBase(N, AM);

  switch (N.getOpcode()) {
  default: