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//===-- SparcJITInfo.cpp - Implement the JIT interfaces for SparcV9 -------===//
//
// The LLVM Compiler Infrastructure
//
// This file was developed by the LLVM research group and is distributed under
// the University of Illinois Open Source License. See LICENSE.TXT for details.
//
//===----------------------------------------------------------------------===//
//
// This file implements the JIT interfaces for the SparcV9 target.
//
//===----------------------------------------------------------------------===//
#define DEBUG_TYPE "jit"
#include "SparcV9JITInfo.h"
#include "SparcV9Relocations.h"
#include "llvm/CodeGen/MachineCodeEmitter.h"
#include "llvm/Config/alloca.h"
#include "llvm/Support/Debug.h"
using namespace llvm;
/// JITCompilerFunction - This contains the address of the JIT function used to
/// compile a function lazily.
static TargetJITInfo::JITCompilerFn JITCompilerFunction;
/// BUILD_SETHI/BUILD_ORI/BUILD_BA/BUILD_CALL - These macros build sparc machine
/// instructions using lots of magic defined by the Sparc ISA.
#define BUILD_SETHI(RD, C) (((RD) << 25) | (4 << 22) | (C & ((1 << 22)-1)))
#define BUILD_ORI(RS, C, RD) ((2 << 30) | (RD << 25) | (2 << 19) | (RS << 14) |\
(1 << 13) | (C & ((1 << 12)-1)))
#define BUILD_BA(DISP) ((8 << 25) | (2 << 22) | (DISP & ((1 << 22)-1)))
#define BUILD_CALL(OFFSET) ((1 << 30) | (OFFSET & (1 << 30)-1))
static void InsertJumpAtAddr(int64_t JumpTarget, unsigned *Addr) {
// If the target function is close enough to fit into the 19bit disp of
// BA, we should use this version, as it's much cheaper to generate.
int64_t BranchTarget = (JumpTarget-(intptr_t)Addr) >> 2;
if (BranchTarget < (1 << 19) && BranchTarget > -(1 << 19)) {
// ba <target>
Addr[0] = BUILD_BA(BranchTarget);
// nop
Addr[1] = 0x01000000;
} else {
enum { G0 = 0, G1 = 1, G5 = 5 };
// Get address to branch into %g1, using %g5 as a temporary
//
// sethi %uhi(Target), %g5 ;; get upper 22 bits of Target into %g5
Addr[0] = BUILD_SETHI(G5, JumpTarget >> 42);
// or %g5, %ulo(Target), %g5 ;; get 10 lower bits of upper word into %1
Addr[1] = BUILD_ORI(G5, JumpTarget >> 32, G5);
// sllx %g5, 32, %g5 ;; shift those 10 bits to the upper word
Addr[2] = 0x8B297020;
// sethi %hi(Target), %g1 ;; extract bits 10-31 into the dest reg
Addr[3] = BUILD_SETHI(G1, JumpTarget >> 10);
// or %g5, %g1, %g1 ;; get upper word (in %g5) into %g1
Addr[4] = 0x82114001;
// or %g1, %lo(Target), %g1 ;; get lowest 10 bits of Target into %g1
Addr[5] = BUILD_ORI(G1, JumpTarget, G1);
// jmpl %g1, %g0, %g0 ;; indirect branch on %g1
Addr[6] = 0x81C00001;
// nop ;; delay slot
Addr[7] = 0x01000000;
}
}
void SparcV9JITInfo::replaceMachineCodeForFunction (void *Old, void *New) {
InsertJumpAtAddr((intptr_t)New, (unsigned*)Old);
}
static void SaveRegisters(uint64_t DoubleFP[], uint64_t CC[],
uint64_t Globals[]) {
#if defined(__sparcv9)
__asm__ __volatile__ (// Save condition-code registers
"stx %%fsr, %0;\n\t"
"rd %%fprs, %1;\n\t"
"rd %%ccr, %2;\n\t"
: "=m"(CC[0]), "=r"(CC[1]), "=r"(CC[2]));
__asm__ __volatile__ (// Save globals g1 and g5
"stx %%g1, %0;\n\t"
"stx %%g5, %0;\n\t"
: "=m"(Globals[0]), "=m"(Globals[1]));
// GCC says: `asm' only allows up to thirty parameters!
__asm__ __volatile__ (// Save Single/Double FP registers, part 1
"std %%f0, %0;\n\t" "std %%f2, %1;\n\t"
"std %%f4, %2;\n\t" "std %%f6, %3;\n\t"
"std %%f8, %4;\n\t" "std %%f10, %5;\n\t"
"std %%f12, %6;\n\t" "std %%f14, %7;\n\t"
"std %%f16, %8;\n\t" "std %%f18, %9;\n\t"
"std %%f20, %10;\n\t" "std %%f22, %11;\n\t"
"std %%f24, %12;\n\t" "std %%f26, %13;\n\t"
"std %%f28, %14;\n\t" "std %%f30, %15;\n\t"
: "=m"(DoubleFP[ 0]), "=m"(DoubleFP[ 1]),
"=m"(DoubleFP[ 2]), "=m"(DoubleFP[ 3]),
"=m"(DoubleFP[ 4]), "=m"(DoubleFP[ 5]),
"=m"(DoubleFP[ 6]), "=m"(DoubleFP[ 7]),
"=m"(DoubleFP[ 8]), "=m"(DoubleFP[ 9]),
"=m"(DoubleFP[10]), "=m"(DoubleFP[11]),
"=m"(DoubleFP[12]), "=m"(DoubleFP[13]),
"=m"(DoubleFP[14]), "=m"(DoubleFP[15]));
__asm__ __volatile__ (// Save Double FP registers, part 2
"std %%f32, %0;\n\t" "std %%f34, %1;\n\t"
"std %%f36, %2;\n\t" "std %%f38, %3;\n\t"
"std %%f40, %4;\n\t" "std %%f42, %5;\n\t"
"std %%f44, %6;\n\t" "std %%f46, %7;\n\t"
"std %%f48, %8;\n\t" "std %%f50, %9;\n\t"
"std %%f52, %10;\n\t" "std %%f54, %11;\n\t"
"std %%f56, %12;\n\t" "std %%f58, %13;\n\t"
"std %%f60, %14;\n\t" "std %%f62, %15;\n\t"
: "=m"(DoubleFP[16]), "=m"(DoubleFP[17]),
"=m"(DoubleFP[18]), "=m"(DoubleFP[19]),
"=m"(DoubleFP[20]), "=m"(DoubleFP[21]),
"=m"(DoubleFP[22]), "=m"(DoubleFP[23]),
"=m"(DoubleFP[24]), "=m"(DoubleFP[25]),
"=m"(DoubleFP[26]), "=m"(DoubleFP[27]),
"=m"(DoubleFP[28]), "=m"(DoubleFP[29]),
"=m"(DoubleFP[30]), "=m"(DoubleFP[31]));
#else
std::cerr << "ERROR: RUNNING CODE THAT ONLY WORKS ON A SPARCV9 HOST!\n";
abort();
#endif
}
static void RestoreRegisters(uint64_t DoubleFP[], uint64_t CC[],
uint64_t Globals[]) {
#if defined(__sparcv9)
__asm__ __volatile__ (// Restore condition-code registers
"ldx %0, %%fsr;\n\t"
"wr %1, 0, %%fprs;\n\t"
"wr %2, 0, %%ccr;\n\t"
:: "m"(CC[0]), "r"(CC[1]), "r"(CC[2]));
__asm__ __volatile__ (// Restore globals g1 and g5
"ldx %0, %%g1;\n\t"
"ldx %0, %%g5;\n\t"
:: "m"(Globals[0]), "m"(Globals[1]));
// GCC says: `asm' only allows up to thirty parameters!
__asm__ __volatile__ (// Restore Single/Double FP registers, part 1
"ldd %0, %%f0;\n\t" "ldd %1, %%f2;\n\t"
"ldd %2, %%f4;\n\t" "ldd %3, %%f6;\n\t"
"ldd %4, %%f8;\n\t" "ldd %5, %%f10;\n\t"
"ldd %6, %%f12;\n\t" "ldd %7, %%f14;\n\t"
"ldd %8, %%f16;\n\t" "ldd %9, %%f18;\n\t"
"ldd %10, %%f20;\n\t" "ldd %11, %%f22;\n\t"
"ldd %12, %%f24;\n\t" "ldd %13, %%f26;\n\t"
"ldd %14, %%f28;\n\t" "ldd %15, %%f30;\n\t"
:: "m"(DoubleFP[0]), "m"(DoubleFP[1]),
"m"(DoubleFP[2]), "m"(DoubleFP[3]),
"m"(DoubleFP[4]), "m"(DoubleFP[5]),
"m"(DoubleFP[6]), "m"(DoubleFP[7]),
"m"(DoubleFP[8]), "m"(DoubleFP[9]),
"m"(DoubleFP[10]), "m"(DoubleFP[11]),
"m"(DoubleFP[12]), "m"(DoubleFP[13]),
"m"(DoubleFP[14]), "m"(DoubleFP[15]));
__asm__ __volatile__ (// Restore Double FP registers, part 2
"ldd %0, %%f32;\n\t" "ldd %1, %%f34;\n\t"
"ldd %2, %%f36;\n\t" "ldd %3, %%f38;\n\t"
"ldd %4, %%f40;\n\t" "ldd %5, %%f42;\n\t"
"ldd %6, %%f44;\n\t" "ldd %7, %%f46;\n\t"
"ldd %8, %%f48;\n\t" "ldd %9, %%f50;\n\t"
"ldd %10, %%f52;\n\t" "ldd %11, %%f54;\n\t"
"ldd %12, %%f56;\n\t" "ldd %13, %%f58;\n\t"
"ldd %14, %%f60;\n\t" "ldd %15, %%f62;\n\t"
:: "m"(DoubleFP[16]), "m"(DoubleFP[17]),
"m"(DoubleFP[18]), "m"(DoubleFP[19]),
"m"(DoubleFP[20]), "m"(DoubleFP[21]),
"m"(DoubleFP[22]), "m"(DoubleFP[23]),
"m"(DoubleFP[24]), "m"(DoubleFP[25]),
"m"(DoubleFP[26]), "m"(DoubleFP[27]),
"m"(DoubleFP[28]), "m"(DoubleFP[29]),
"m"(DoubleFP[30]), "m"(DoubleFP[31]));
#else
std::cerr << "ERROR: RUNNING CODE THAT ONLY WORKS ON A SPARCV9 HOST!\n";
abort();
#endif
}
static void CompilationCallback() {
// Local space to save the registers
uint64_t DoubleFP[32];
uint64_t CC[3];
uint64_t Globals[2];
SaveRegisters(DoubleFP, CC, Globals);
unsigned *CameFrom = (unsigned*)<
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