path: root/lib/Target/ARM/AsmPrinter/ARMInstPrinter.cpp

//===-- ARMInstPrinter.cpp - Convert ARM MCInst to assembly syntax --------===//
//
//                     The LLVM Compiler Infrastructure
//
// This file is distributed under the University of Illinois Open Source
// License. See LICENSE.TXT for details.
//
//===----------------------------------------------------------------------===//
//
// This class prints an ARM MCInst to a .s file.
//
//===----------------------------------------------------------------------===//

#define DEBUG_TYPE "asm-printer"
#include "ARM.h" // FIXME: FACTOR ENUMS BETTER.
#include "ARMInstPrinter.h"
#include "ARMAddressingModes.h"
#include "llvm/MC/MCInst.h"
#include "llvm/MC/MCAsmInfo.h"
#include "llvm/MC/MCExpr.h"
#include "llvm/ADT/StringExtras.h"
#include "llvm/Support/raw_ostream.h"
using namespace llvm;

// Include the auto-generated portion of the assembly writer.
#define MachineInstr MCInst
#define ARMAsmPrinter ARMInstPrinter  // FIXME: REMOVE.
#include "ARMGenAsmWriter.inc"
#undef MachineInstr
#undef ARMAsmPrinter

static unsigned NextReg(unsigned Reg) {
  switch (Reg) {
  default:
    assert(0 && "Unexpected register enum");

  case ARM::D0:
    return ARM::D1;
  case ARM::D1:
    return ARM::D2;
  case ARM::D2:
    return ARM::D3;
  case ARM::D3:
    return ARM::D4;
  case ARM::D4:
    return ARM::D5;
  case ARM::D5:
    return ARM::D6;
  case ARM::D6:
    return ARM::D7;
  case ARM::D7:
    return ARM::D8;
  case ARM::D8:
    return ARM::D9;
  case ARM::D9:
    return ARM::D10;
  case ARM::D10:
    return ARM::D11;
  case ARM::D11:
    return ARM::D12;
  case ARM::D12:
    return ARM::D13;
  case ARM::D13:
    return ARM::D14;
  case ARM::D14:
    return ARM::D15;
  case ARM::D15:
    return ARM::D16;
  case ARM::D16:
    return ARM::D17;
  case ARM::D17:
    return ARM::D18;
  case ARM::D18:
    return ARM::D19;
  case ARM::D19:
    return ARM::D20;
  case ARM::D20:
    return ARM::D21;
  case ARM::D21:
    return ARM::D22;
  case ARM::D22:
    return ARM::D23;
  case ARM::D23:
    return ARM::D24;
  case ARM::D24:
    return ARM::D25;
  case ARM::D25:
    return ARM::D26;
  case ARM::D26:
    return ARM::D27;
  case ARM::D27:
    return ARM::D28;
  case ARM::D28:
    return ARM::D29;
  case ARM::D29:
    return ARM::D30;
  case ARM::D30:
    return ARM::D31;
  }
}

void ARMInstPrinter::printInst(const MCInst *MI, raw_ostream &O) {
  // Check for MOVs and print canonical forms, instead.
  if (MI->getOpcode() == ARM::MOVs) {
    const MCOperand &Dst = MI->getOperand(0);
    const MCOperand &MO1 = MI->getOperand(1);
    const MCOperand &MO2 = MI->getOperand(2);
    const MCOperand &MO3 = MI->getOperand(3);

    O << '\t' << ARM_AM::getShiftOpcStr(ARM_AM::getSORegShOp(MO3.getImm()));
    printSBitModifierOperand(MI, 6, O);
    printPredicateOperand(MI, 4, O);

    O << '\t' << getRegisterName(Dst.getReg())
      << ", " << getRegisterName(MO1.getReg());

    if (ARM_AM::getSORegShOp(MO3.getImm()) == ARM_AM::rrx)
      return;

    O << ", ";

    if (MO2.getReg()) {
      O << getRegisterName(MO2.getReg());
      assert(ARM_AM::getSORegOffset(MO3.getImm()) == 0);
    } else {
      O << "#" << ARM_AM::getSORegOffset(MO3.getImm());
    }
    return;
  }

  // A8.6.123 PUSH
  if ((MI->getOpcode() == ARM::STM_UPD || MI->getOpcode() == ARM::t2STM_UPD) &&
      MI->getOperand(0).getReg() == ARM::SP) {
    const MCOperand &MO1 = MI->getOperand(2);
    if (ARM_AM::getAM4SubMode(MO1.getImm()) == ARM_AM::db) {
      O << '\t' << "push";
      printPredicateOperand(MI, 3, O);
      O << '\t';
      printRegisterList(MI, 5, O);
      return;
    }
  }

  // A8.6.122 POP
  if ((MI->getOpcode() == ARM::LDM_UPD || MI->getOpcode() == ARM::t2LDM_UPD) &&
      MI->getOperand(0).getReg() == ARM::SP) {
    const MCOperand &MO1 = MI->getOperand(2);
    if (ARM_AM::getAM4SubMode(MO1.getImm()) == ARM_AM::ia) {
      O << '\t' << "pop";
      printPredicateOperand(MI, 3, O);
      O </