path: root/lib/Target/ARM/ARMInstrThumb.td

//===- ARMInstrThumb.td - Thumb support for ARM ------------*- tablegen -*-===//
//
//                     The LLVM Compiler Infrastructure
//
// This file is distributed under the University of Illinois Open Source
// License. See LICENSE.TXT for details.
//
//===----------------------------------------------------------------------===//
//
// This file describes the Thumb instruction set.
//
//===----------------------------------------------------------------------===//

//===----------------------------------------------------------------------===//
// Thumb specific DAG Nodes.
//

def ARMtcall : SDNode<"ARMISD::tCALL", SDT_ARMcall,
                      [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue,
                       SDNPVariadic]>;

def imm_neg_XFORM : SDNodeXForm<imm, [{
  return CurDAG->getTargetConstant(-(int)N->getZExtValue(), MVT::i32);
}]>;
def imm_comp_XFORM : SDNodeXForm<imm, [{
  return CurDAG->getTargetConstant(~((uint32_t)N->getZExtValue()), MVT::i32);
}]>;

def imm0_7_neg : PatLeaf<(i32 imm), [{
  return (uint32_t)-N->getZExtValue() < 8;
}], imm_neg_XFORM>;

def imm0_255_asmoperand : AsmOperandClass { let Name = "Imm0_255"; }
def imm0_255 : Operand<i32>, ImmLeaf<i32, [{ return Imm >= 0 && Imm < 256; }]> {
  let ParserMatchClass = imm0_255_asmoperand;
}
def imm0_255_comp : PatLeaf<(i32 imm), [{
  return ~((uint32_t)N->getZExtValue()) < 256;
}]>;

def imm8_255 : ImmLeaf<i32, [{
  return Imm >= 8 && Imm < 256;
}]>;
def imm8_255_neg : PatLeaf<(i32 imm), [{
  unsigned Val = -N->getZExtValue();
  return Val >= 8 && Val < 256;
}], imm_neg_XFORM>;

// Break imm's up into two pieces: an immediate + a left shift. This uses
// thumb_immshifted to match and thumb_immshifted_val and thumb_immshifted_shamt
// to get the val/shift pieces.
def thumb_immshifted : PatLeaf<(imm), [{
  return ARM_AM::isThumbImmShiftedVal((unsigned)N->getZExtValue());
}]>;

def thumb_immshifted_val : SDNodeXForm<imm, [{
  unsigned V = ARM_AM::getThumbImmNonShiftedVal((unsigned)N->getZExtValue());
  return CurDAG->getTargetConstant(V, MVT::i32);
}]>;

def thumb_immshifted_shamt : SDNodeXForm<imm, [{
  unsigned V = ARM_AM::getThumbImmValShift((unsigned)N->getZExtValue());
  return CurDAG->getTargetConstant(V, MVT::i32);
}]>;

// ADR instruction labels.
def t_adrlabel : Operand<i32> {
  let EncoderMethod = "getThumbAdrLabelOpValue";
}

// Scaled 4 immediate.
def t_imm_s4 : Operand<i32> {
  let PrintMethod = "printThumbS4ImmOperand";
  let OperandType = "OPERAND_IMMEDIATE";
}

// Define Thumb specific addressing modes.

let OperandType = "OPERAND_PCREL" in {
def t_brtarget : Operand<OtherVT> {
  let EncoderMethod = "getThumbBRTargetOpValue";
}

def t_bcctarget : Operand<i32> {
  let EncoderMethod = "getThumbBCCTargetOpValue";
}

def t_cbtarget : Operand<i32> {
  let EncoderMethod = "getThumbCBTargetOpValue";
}

def t_bltarget : Operand<i32> {
  let EncoderMethod = "getThumbBLTargetOpValue";
}

def t_blxtarget : Operand<i32> {
  let EncoderMethod = "getThumbBLXTargetOpValue";
}
}

def MemModeRegThumbAsmOperand : AsmOperandClass {
  let Name = "MemModeRegThumb";
  let SuperClasses = [];
}

def MemModeImmThumbAsmOperand : AsmOperandClass {
  let Name = "MemModeImmThumb";
  let SuperClasses = [];
}

// t_addrmode_rr := reg + reg
//
def t_addrmode_rr : Operand<i32>,
                    ComplexPattern<i32, 2, "SelectThumbAddrModeRR", []> {
  let EncoderMethod = "getThumbAddrModeRegRegOpValue";
  let PrintMethod = "printThumbAddrModeRROperand";
  let MIOperandInfo = (ops tGPR:$base, tGPR:$offsreg);
}

// t_addrmode_rrs := reg + reg
//
def t_addrmode_rrs1 : Operand<i32>,
                      ComplexPattern<i32, 2, "SelectThumbAddrModeRI5S1", []> {
  let EncoderMethod = "getThumbAddrModeRegRegOpValue";
  let PrintMethod = "printThumbAddrModeRROperand";
  let MIOperandInfo = (ops tGPR:$base, tGPR:$offsreg);
  let ParserMatchClass = MemModeRegThumbAsmOperand;
}
def t_addrmode_rrs2 : Operand<i32>,
                      ComplexPattern<i32, 2, "SelectThumbAddrModeRI5S2", []> {
  let EncoderMethod = "getThumbAddrModeRegRegOpValue";
  let PrintMethod = "printThumbAddrModeRROperand";
  let MIOperandInfo = (ops tGPR:$base, tGPR:$offsreg);
  let ParserMatchClass = MemModeRegThumbAsmOperand;
}
def t_addrmode_rrs4 : Operand<i32>,
                      ComplexPattern<i32, 2, "SelectThumbAddrModeRI5S4", []> {
  let EncoderMethod = "getThumbAddrModeRegRegOpValue";
  let PrintMethod = "printThumbAddrModeRROperand";
  let MIOperandInfo = (ops tGPR:$base, tGPR:$offsreg);
  let ParserMatchClass = MemModeRegThumbAsmOperand;
}

// t_addrmode_is4 := reg + imm5 * 4
//
def t_addrmode_is4 : Operand<i32>,
                     ComplexPattern<i32, 2, "SelectThumbAddrModeImm5S4", []> {
  let EncoderMethod = "getAddrModeISOpValue";
  let PrintMethod = "printThumbAddrModeImm5S4Operand";
  let MIOperandInfo = (ops tGPR:$base, i32imm:$offsimm);
  let ParserMatchClass = MemModeImmThumbAsmOperand;
}

// t_addrmode_is2 := reg + imm5 * 2
//
def t_addrmode_is2 : Operand<i32>,
                     ComplexPattern<i32, 2, "SelectThumbAddrModeImm5S2", []> {
  let EncoderMethod = "getAddrModeISOpValue";
  let PrintMethod = "printThumbAddrModeImm5S2Operand";
  let MIOperandInfo = (ops tGPR:$base, i32imm:$offsimm);
  let ParserMatchClass = MemModeImmThumbAsmOperand;
}

// t_addrmode_is1 := reg + imm5
//
def t_addrmode_is1 : Operand<i32>,
                     ComplexPattern<i32, 2, "SelectThumbAddrModeImm5S1", []> {
  let EncoderMethod = "getAddrModeISOpValue";
  let PrintMethod = "printThumbAddrModeImm5S1Operand";
  let MIOperandInfo = (ops tGPR:$base, i32imm:$offsimm);
  let ParserMatchClass = MemModeImmThumbAsmOperand;
}

// t_addrmode_sp := sp + imm8 * 4
//
def t_addrmode_sp : Operand<i32>,
                    ComplexPattern<i32, 2, "SelectThumbAddrModeSP", []> {
  let EncoderMethod = "getAddrModeThumbSPOpValue";
  let PrintMethod = "printThumbAddrModeSPOperand";
  let MIOperandInfo = (ops GPR:$base, i32imm:$offsimm);
  let ParserMatchClass = MemModeImmThumbAsmOperand;
}

// t_addrmode_pc := <label> => pc + imm8 * 4
//
def t_addrmode_pc : Operand<i32> {
  let EncoderMethod = "getAddrModePCOpValue";
  let ParserMatchClass = MemModeImmThumbAsmOperand;
}

//===----------------------------------------------------------------------===//
//  Miscellaneous Instructions.
//

// FIXME: Marking these as hasSideEffects is necessary to prevent machine DCE
// from removing one half of the matched pairs. That breaks PEI, which assumes
// these will always be in pairs, and asserts if it finds otherwise. Better way?
let Defs = [SP], Uses = [SP], hasSideEffects = 1 in {
def tADJCALLSTACKUP :
  PseudoInst<(outs), (ins i32imm:$amt1, i32imm:$amt2), NoItinerary,
             [(ARMcallseq_end imm:$amt1, imm:$amt2)]>,
            Requires<[IsThumb, IsThumb1Only]>;

def tADJCALLSTACKDOWN :
  PseudoInst<(outs), (ins i32imm:$amt), NoItinerary,
             [(ARMcallseq_start imm:$amt)]>,
            Requires<[IsThumb, IsThumb1Only]>;
}

// T1Disassembly - A simple class to make encoding some disassembly patterns
// easier and l