1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
|
//===-- ARM.h - Top-level interface for ARM representation---- --*- C++ -*-===//
//
// The LLVM Compiler Infrastructure
//
// This file was developed by the "Instituto Nokia de Tecnologia" and
// is distributed under the University of Illinois Open Source
// License. See LICENSE.TXT for details.
//
//===----------------------------------------------------------------------===//
//
// This file contains the entry points for global functions defined in the LLVM
// ARM back-end.
//
//===----------------------------------------------------------------------===//
#ifndef TARGET_ARM_H
#define TARGET_ARM_H
#include <iosfwd>
#include <cassert>
namespace llvm {
// Enums corresponding to ARM condition codes
namespace ARMCC {
enum CondCodes {
EQ,
NE,
CS,
CC,
MI,
PL,
VS,
VC,
HI,
LS,
GE,
LT,
GT,
LE,
AL
};
}
namespace ARMShift {
enum ShiftTypes {
LSL,
LSR,
ASR,
ROR,
RRX
};
}
static const char *ARMCondCodeToString(ARMCC::CondCodes CC) {
switch (CC) {
default: assert(0 && "Unknown condition code");
case ARMCC::EQ: return "eq";
case ARMCC::NE: return "ne";
case ARMCC::CS: return "cs";
case ARMCC::CC: return "cc";
case ARMCC::MI: return "mi";
case ARMCC::PL: return "pl";
case ARMCC::VS: return "vs";
case ARMCC::VC: return "vc";
case ARMCC::HI: return "hi";
case ARMCC::LS: return "ls";
case ARMCC::GE: return "ge";
case ARMCC::LT: return "lt";
case ARMCC::GT: return "gt";
case ARMCC::LE: return "le";
case ARMCC::AL: return "al";
}
}
class FunctionPass;
class TargetMachine;
FunctionPass *createARMISelDag(TargetMachine &TM);
FunctionPass *createARMCodePrinterPass(std::ostream &OS, TargetMachine &TM);
FunctionPass *createARMFixMulPass();
} // end namespace llvm;
// Defines symbolic names for ARM registers. This defines a mapping from
// register name to register number.
//
#include "ARMGenRegisterNames.inc"
// Defines symbolic names for the ARM instructions.
//
#include "ARMGenInstrNames.inc"
#endif
|
