path: root/include/llvm/Target/TargetInstrInfo.h

//===-- llvm/Target/TargetInstrInfo.h - Instruction Info --------*- C++ -*-===//
// 
//                     The LLVM Compiler Infrastructure
//
// This file was developed by the LLVM research group and is distributed under
// the University of Illinois Open Source License. See LICENSE.TXT for details.
// 
//===----------------------------------------------------------------------===//
//
// This file describes the target machine instructions to the code generator.
//
//===----------------------------------------------------------------------===//

#ifndef LLVM_TARGET_TARGETINSTRINFO_H
#define LLVM_TARGET_TARGETINSTRINFO_H

#include "Support/DataTypes.h"
#include <vector>
#include <cassert>

namespace llvm {

class MachineInstr;
class TargetMachine;
class Value;
class Type;
class Instruction;
class Constant;
class Function;
class MachineCodeForInstruction;

//---------------------------------------------------------------------------
// Data types used to define information about a single machine instruction
//---------------------------------------------------------------------------

typedef int MachineOpCode;
typedef unsigned InstrSchedClass;

const MachineOpCode INVALID_MACHINE_OPCODE = -1;


//---------------------------------------------------------------------------
// struct TargetInstrDescriptor:
//	Predefined information about each machine instruction.
//	Designed to initialized statically.
//

const unsigned M_NOP_FLAG		= 1 << 0;
const unsigned M_BRANCH_FLAG		= 1 << 1;
const unsigned M_CALL_FLAG		= 1 << 2;
const unsigned M_RET_FLAG		= 1 << 3;
const unsigned M_ARITH_FLAG		= 1 << 4;
const unsigned M_CC_FLAG		= 1 << 6;
const unsigned M_LOGICAL_FLAG		= 1 << 6;
const unsigned M_INT_FLAG		= 1 << 7;
const unsigned M_FLOAT_FLAG		= 1 << 8;
const unsigned M_CONDL_FLAG		= 1 << 9;
const unsigned M_LOAD_FLAG		= 1 << 10;
const unsigned M_PREFETCH_FLAG		= 1 << 11;
const unsigned M_STORE_FLAG		= 1 << 12;
const unsigned M_DUMMY_PHI_FLAG	= 1 << 13;
const unsigned M_PSEUDO_FLAG           = 1 << 14;       // Pseudo instruction
// 3-addr instructions which really work like 2-addr ones, eg. X86 add/sub
const unsigned M_2_ADDR_FLAG           = 1 << 15;

// M_TERMINATOR_FLAG - Is this instruction part of the terminator for a basic
// block?  Typically this is things like return and branch instructions.
// Various passes use this to insert code into the bottom of a basic block, but
// before control flow occurs.
const unsigned M_TERMINATOR_FLAG       = 1 << 16;

struct TargetInstrDescriptor {
  const char *    Name;          // Assembly language mnemonic for the opcode.
  int             numOperands;   // Number of args; -1 if variable #args
  int             resultPos;     // Position of the result; -1 if no result
  unsigned        maxImmedConst; // Largest +ve constant in IMMED field or 0.
  bool	          immedIsSignExtended; // Is IMMED field sign-extended? If so,
                                 //   smallest -ve value is -(maxImmedConst+1).
  unsigned        numDelaySlots; // Number of delay slots after instruction
  unsigned        latency;       // Latency in machine cycles
  InstrSchedClass schedClass;    // enum  identifying instr sched class
  unsigned        Flags;         // flags identifying machine instr class
  unsigned        TSFlags;       // Target Specific Flag values
  const unsigned *ImplicitUses;  // Registers implicitly read by this instr
  const unsigned *ImplicitDefs;  // Registers implicitly defined by this instr
};


//---------------------------------------------------------------------------
/// 
/// TargetInstrInfo - Interface to description of machine instructions
/// 
class TargetInstrInfo {
  const TargetInstrDescriptor* desc;    // raw array to allow static init'n
  unsigned descSize;                    // number of entries in the desc array
  unsigned numRealOpCodes;              // number of non-dummy op codes
  
  TargetInstrInfo(const TargetInstrInfo &);  // DO NOT IMPLEMENT
  void operator=(const TargetInstrInfo &);   // DO NOT IMPLEMENT
public:
  TargetInstrInfo(const TargetInstrDescriptor *desc, unsigned descSize,
		  unsigned numRealOpCodes);
  virtual ~TargetInstrInfo();

  // Invariant: All instruction sets use opcode #0 as the PHI instruction
  enum { PHI = 0 };
  
  unsigned getNumRealOpCodes()  const { return numRealOpCodes; }
  unsigned getNumTotalOpCodes() const { return descSize; }
  
  /// get - Return the machine instruction descriptor that corresponds to the
  /// specified instruction opcode.
  ///
  const TargetInstrDescriptor& get(MachineOpCode opCode) const {
    assert(opCode >= 0 && opCode < (int)descSize);
    return desc[opCode];
  }

  const char *getName(MachineOpCode opCode) const {
    return get(opCode).Name;
  }
  
  int getNumOperands(MachineOpCode opCode) const {
    return get(opCode).numOperands;
  }
  
  int getResultPos(MachineOpCode opCode) const {
    return get(opCode).resultPos;
  }
  
  unsigned getNumDelaySlots(MachineOpCode opCode) const {
    return get(opCode).numDelaySlots;
  }
  
  InstrSchedClass getSchedClass(MachineOpCode opCode) const {
    return get(opCode).schedClass;
  }

  const unsigned *getImplicitUses(MachineOpCode opCode) const {
    return get(opCode).ImplicitUses;
  }

  const unsigned *getImplicitDefs(MachineOpCode opCode) const {
    return get(opCode).ImplicitDefs;
  }

  //
  // Query instruction class flags according to the machine-independent
  // flags listed above.
  // 
  bool isNop(MachineOpCode opCode) const {
    return get(opCode).Flags & M_NOP_FLAG;
  }
  bool isBranch(MachineOpCode opCode) const {
    return get(opCode).Flags & M_BRANCH_FLAG;
  }
  bool isCall(MachineOpCode opCode) const {
    return get(opCode).Flags & M_CALL_FLAG;
  }
  bool isReturn(MachineOpCode opCode) const {
    return get(opCode).Flags & M_RET_FLAG;
  }
  bool isControlFlow(MachineOpCode opCode) const {
    return get(opCode).Flags & M_BRANCH_FLAG
        || get(opCode).Flags & M_CALL_FLAG
        || get(opCode).Flags & M_RET_FLAG;
  }
  bool isArith(MachineOpCode opCode) const {
    return get(opCode).Flags & M_ARITH_FLAG;
  }
  bool isCCInstr(MachineOpCode opCode) const {
    return get(opCode).Flags & M_CC_FLAG;
  }
  bool isLogical(MachineOpCode opCode) const {
    return get(opCode).Flags & M_LOGICAL_FLAG;
  }
  bool isIntInstr(MachineOpCode opCode) const {
    return get(opCode).Flags & M_INT_FLAG;
  }
  bool isFloatInstr(MachineOpCode opCode) const {
    return get(opCode).Flags & M_FLOAT_FLAG;
  }
  bool isConditional(MachineOpCode opCode) const { 
    return get(opCode).Flags & M_CONDL_FLAG;
  }
  bool isLoad(MachineOpCode opCode) const {
    return get(opCode).Flags & M_LOAD_FLAG;
  }
  bool isPrefetch(MachineOpCode opCode) const {
    return get(opCode).Flags & M_PREFETCH_FLAG;
  }
  bool isLoadOrPrefetch(MachineOpCode opCode) const {
    return get(opCode).Flags & M_LOAD_FLAG
        || get(opCode).Flags & M_PREFETCH_FLAG;
  }
  bool isStore(MachineOpCode opCode) const {
    return get(opCode).Flags & M_STORE_FLAG;
  }
  bool isMemoryAccess(MachineOpCode opCode) const {
    return get(opCode).Flags & M_LOAD_FLAG
        || get(opCode).Flags & M_PREFETCH_FLAG
        || get(opCode).Flags & M_STORE_FLAG;
  }
  bool isDummyPhiInstr(MachineOpCode opCode) const {
    return get(opCode).Flags & M_DUMMY_PHI_FLAG;
  }
  bool isPseudoInstr(MachineOpCode opCode) const {
    return get(opCode).Flags & M_PSEUDO_FLAG;
  }
  bool isTwoAddrInstr(MachineOpCode opCode) const {
    return get(opCode).Flags & M_2_ADDR_FLAG;
  }
  bool isTerminatorInstr(unsigned Opcode) const {
    return get(Opcode).Flags &